High-Speed High-Precision CMOS Current Conveyor

In this paper a new class-AB CMOS second generation current conveyor (CCII) based on a novel high-performance voltage follower topology is proposed. Post-layout simulation results from a 0.8 m design supplied at 3.3 V show very low resistance at node X (<50 ), high frequency operation (100 MHz), high precision in the voltage and current transference and reduced offset. As application examples, a V-I converter and a current feedback operational amplifier (CFOA) have been implemented. The latter presents slew-rate levels higher than ±100 V/s.     

A Self-Calibrated Pipeline ADC with 200 MHz IF-Sampling Frontend

A 13-bit, 50-MS/s pipeline ADC with IF-sampling capability is presented. A high sampling linearity is obtained through the use of bootstrapped switches. A digital self-calibration algorithm with modified capacitor measurement scheme is employed to improve the accuracy of the first two pipeline stages. The prototype, implemented with a 0.35-m BiCMOS (SiGe) technology, shows a 76.5-dB SFDR at a 194.2-MHz signal frequency and dissipates 715 mW power from a 2.9-V supply.     

A High Speed, Low Voltage CMOS Offset Comparator

A high speed, low voltage offset comparator is presented. No common mode tracking circuit is used and the offset is added without compromising the high input impedance nature of the circuit. The circuit operates at 480 Mbps with 3.0–3.6 V and 1.6–2.0 V supplies and –40 to 125°C temperature range on a typical 0.5 m technology.     

F-TRIA01: A Fast Bipolar Transimpedance Amplifier

This paper describes a new transimpedance amplifier for fast current pulses delivered by high energy particle detectors. The choice of a bipolar technology allowed a 100 low input impedance and a rise time down to 1 nS. The fully differential current mode architecture provides an excellent linearity and a large versatility as for its transimpedance, bandwidth and power consumption.     

CMOS Analog Implementation of a Discrete-Time 9-Tap FIR Filter with Circular Buffer Architecture

This paper presents the design and simulation of a 9-Tap CMOS Analog Discrete-Time Finite Impulse Response (FIR) Filter system. This unique design features a Circular Buffer Architecture which achieves high sampling rate that can be easily expanded to improve speed and extended to higher order filters. Novel area-efficient four quadrant CMOS analog adder and multiplier circuits are employed to respond for high frequency and wide linear range inputs. The layout for all circuits has been realized using the design tool MAGIC with a 1.2 m CMOS process. The performance for each circuit and the whole system are characterized using HSPICE simulation based on the extracted MAGIC netlist. The 9-tap filter was designed to achieve 5 MHz sampling rate. The implemented design requires a total chip area of 1690.9 m by 2134.2 m and ±5 volt power supply.     

对于电子信息类专业课程内容与设置的几点意见

本文对电子信息类专业课程提出了软件与硬件、模拟电路与数字电路均应并重的观点,并建议增设“电工学”课程。     

电流控阈技术及三值电流型 CMOS施密特电路

本文以开关信号理论为指导 ,对电流型 CM OS电路中如何实现阈值控制进行研究. 建立实现阈 值控制电路的电流传输开关运算 ,并用于指导电流型 CMOS施密特电路的开关级设计 .用 PSPICE程序 模拟证明了所设计的电路具有理想的施密特电路特性.     

Photonic crystal channel drop filters with mirror cavities

In this paper, a new channel drop filter in two dimensional photonic crystals with mirror cavities is proposed. In the structure, three cavities are used. One is used for a resonant tunneling-based channel drop filter. The others are used to realize reflection feedback in the bus waveguide, which consists of a point defect micro-cavity side-coupled to a waveguide. The simulation results by using the finite-difference time-domain method conclude 98% output efficiency.     

1.5V工作电压带隙基准电路的设计

在分析传统带隙基准电路的基础上,提出一种采用电流模式结构的低电压带隙基准电路。该电路能够输出200mV~1.25V的宽范围的电压,并使用了与电源无关偏置以及带负反馈网络的二级运放,提高了输出电压的精度。采用CMOS0.35μm工艺实现时,工作电压可在1.1V~1.5V。Hspice仿真结果表明,工作电压为1.5V时,电路的有效温度系数为14ppm/℃。     

数模混合电路的PCB设计

高速PCB的设计中,数模混合电路的PCB设计中的干扰问题一直是一个难题。尤其模拟电路一般是信号的源头,能否正确接收和转换信号是PCB设计要考虑的重要因素。文章通过分析混合电路干扰产生的机理,结合设计实践,探讨了混合电路一般处理方法,并通过设计实例得到验证。