WiGig and IEEE 802.11ad for Multi-Gigabyte- Per-Second WPAN and WLAN

The Wireless Gigabit Alliance (WiGig) and IEEE 802.11ad are developing a multigigabit wireless personal and local area network (WPAN/WLAN) specification in the 60 GHz millimeter wave band. Chipset manufacturers, original equipment manufacturers (OEMs), and telecom companies are also assisting in this development. 60 GHz millimeter wave transmission will scale the speed of WLANs and WPANs to 6.75 Gbit/s over distances less than 10 meters. This technology is the first of its kind and will eliminate the need for cable around personal computers, docking stations, and other consumer electronic devices. High-definition multimedia interface (HDMI), display port, USB 3.0, and peripheral component interconnect express (PCIe) 3.0 cables will all be eliminated. Fast downloads and uploads, wireless sync, and multi-gigabit-per-second WLANs will be possible over shorter distances. 60 GHz millimeter wave supports fast session transfer (FST) protocol, which makes it backward compatible with 5 GHz or 2.4 GHz WLAN so that end users experience the same range as in today’s WLANs. IEEE 802.11ad specifies the physical (PHY) sublayer and medium access control (MAC) sublayer of the protocol stack. The MAC protocol is based on time-division multiple access (TDMA), and the PHY layer uses single carrier (SC) and orthogonal frequency division multiplexing (OFDM) to simultaneously enable low-power, high-performance applications.     

Negative Save Sign Extension for Multi-term Adders and Multipliers

This paper outlines a new sign extension technique for use in carry save adder trees that reduces the computational complexity. The “Negative Save” technique presented is a modification to the Baugh–Wooley sign extension technique developed for array multipliers. Applying this sign extension technique to both parallel adder and multiplier partial product structures reduces the hardware required. The speed of the resulting structures is also improved.

通信局房电源区域规划建设研究

为解决通信局房传统电源建设模式存在的资源浪费等问题,通过调查研究,文章提出了电源区域规划建设模式。该模式结合传统电源建设模式,解决了电源设备利用率不高问题,达到节能、节约设备投资和节约机房面积的效果,同时其符合电源建设安全性和可扩展性原则,可应用于通信局房的电源规划和动力资源优化建设。     

Low power and high speed multiplier design with row bypassing and parallel architecture

This paper presents a low power and high speed row bypassing multiplier. The primary power reductions are obtained by tuning off MOS components through multiplexers when the operands of multiplier are zero. Analysis of the conventional DSP applications shows that the average of zero input of operand in multiplier is 73.8 percent. Therefore, significant power consumption can be reduced by the proposed bypassing multiplier. The proposed multiplier adopts ripple-carry adder with fewer additional hardware components. In addition, the proposed bypassing architecture can enhance operating speed by the additional parallel architecture to shorten the delay time of the proposed multiplier. Both unsigned and signed operands of multiplier are developed. Post-layout simulations are performed with standard TSMC 0.18 μm CMOS technology and 1.8 V supply voltage by Cadence Spectre simulation tools. Simulation results show that the proposed design can reduce power consumption and operating speed compared to those of counterparts. For a 16×16 multiplier, the proposed design achieves 17 and 36 percent reduction in power consumption and delay, respectively, at the cost of 20 percent increase of chip area in comparison with those of conventional array multipliers. In addition, the proposed design achieves averages of 11 and 38 percent reduction in power consumption and delay with 46 percent less chip area in comparison with those counterparts for both unsigned and signed multipliers. The proposed design is suitable for low power and high speed arithmetic applications.     

The Application of Chitosan Nanostructures in Stomatology

Chitosan (CS) is a natural polymer with a positive charge, a deacetylated derivative of chitin. Chitosan nanostructures (nano-CS) have received increasing interest due to their potential applications and remarkable properties. They offer advantages in stomatology due to their excellent biocompatibility, their antibacterial properties, and their biodegradability. Nano-CSs can be applied as drug carriers for soft tissue diseases, bone tissue engineering and dental hard tissue remineralization; furthermore, they have been used in endodontics due to their antibacterial properties; and, finally, nano-CS can improve the adhesion and mechanical properties of dental-restorative materials due to their physical blend and chemical combinations. In this review, recent developments in the application of nano-CS for stomatology are summarized, with an emphasis on nano-CS’s performance characteristics in different application fields. Moreover, the challenges posed by and the future trends in its application are assessed.     

一种采用四/五输入可配置查找表结构和优化进位链的新型FPGA

本文提出了一种FPGA可编程逻辑单元中新型的查找表结构和进位链结构。查找表被设计为同时支持四输入和五输入的结构,可根据用户需要进行配置,且不增加使用的互连资源;在新型的进位链中针对关键路径进行了优化。最后在可配置逻辑单元中插入了新设计的可配置扫描链。该可编程逻辑单元电路采用0.13μm 1P8M 1.2/2.5/3.3V Logic CMOS工艺制造。测试结果显示可正确实现四/五输入查找表功能,且进位链传播前级进位的速度在同一工艺下较传统进位链结构提高了约3倍,同时整个可编程逻辑单元的面积较之前增大了72.5%。结果还显示,本文设计的FPGA在仅使用四输入查找表时,逻辑资源利用率高于Virtex II/Virtex 4/Virtex 5/Virtex 6/Virtex 7系列FPGA;在仅使用五输入查找表时,逻辑资源利用率高于Virtex II/Virtex 4系列FPGA。     

成对载波多址系统中干扰信号幅度的估计

导出了成对载波多址(PCMA)系统中干扰信号幅度估计的克拉美-罗不等式，提出了一种适合于PCMA系统的干扰信号幅度的估计算法，并对其性能进行了仿真。仿真结果表明，文中提出改进的估计器性能在较高值噪比下接近克拉美-罗不等式。     

基于逻辑结构的超前进位加法器的设计

通过对计算机加法器的研究,从门电路标准延迟模型出发,在对超前进位加法器逻辑公式研究的基础上,在主要考虑速度的前提下,给出了超前进位加法器的逻辑电路的设计方案。主要对16位、32位加法器的逻辑电路进行分析设计,通过计算加法器的延迟时间来对比超前进位加法器与传统串行进位链加法器,得出超前进位算法在实际电路中使加法器的运算速度达到最优。     

Energy efficient hybrid adder architecture

An energy efficient adder design based on a hybrid carry computation is proposed. Addition takes place by considering the carry as propagating forwards from the LSB and backwards from the MSB. The incidence at a midpoint significantly accelerates the addition. This acceleration together with combining low-cost ripple-carry and carry-chain circuits, yields energy efficiency compared to other adder architectures. The optimal midpoint is analytically formulated and its closed-form expression is derived. To avoid the quadratic RC delay growth in a long carry chain, it is optimally repeated. The adder is enhanced in a tree-like structure for further acceleration. 32, 64 and 128-bit adders targeting 500 MHz and 1 GHz clock frequencies were designed in 65 nm technology. They consumed 11–18% less energy compared to adders generated by state-of-the-art EDA synthesis tool.     

可综合算术运算单元的性能建模及VLSI结构优化

提出了一种可综合算术运算单元的性能评估与建模方法.该方法以单位门面积及延迟模型为基础,在设计的早期即可估算电路的面积、延迟等性能指标,从而便于设计者进行VLSI结构的优化,避免设计叠代;并以算术运算中最典型的二进制加法器为例,研究如何利用该模型对电路的VLSI实现结构进行评估、优化;理论分析的结论与电路的实现结果吻合,验证了该方法的有效性.