有界变量线性规划的基线算法

本文对有界变量线性规划的算法进行了研究，得到了一种解此问题的新算法。文中根据基线算法的算法原理，通过对BL表的旋转，在各变量满足界约束的条件下，使目标函数值不断增大，直至得到有界硬上界，从而得到问题的最优解。文中给出了有界变量线性规划基线算法的计算步骤，并给出了一个例子。与单纯形法相比，采用基线算法解有界变量线性规划操作更简单。迭代次数少，解题速度更快。     

基于MATLAB语言的自动控制原理多媒体教学研究

结合我校自动化专业教学，从培养高素质，复合型人才的角度，在教学中引入目前世界上流行的MATLAB软件，并把MATLAB语言应用于经典控制系统设计和分析中，在自动控制原理多媒体辅助教学方面做了一些有益尝试和探索，取得了满意的教学效果。     

一类无穷下三角矩阵的代数性质

修正了 [4,5]中的 Jabotinsky矩阵,得到并证明了一类无穷下三角矩阵T（f）的一些性质,最后,导出了一些与导数相关的反演关系和组合恒等式.     

CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing

As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features.This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundray Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation.These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A tool-box environment is provided, in order to automatically generate the needed component to build the chosen SoC test architecture.     

大功率晶体管的保护电路

大功率晶体管调速系统中作为开关元件使用时，共优点是开关频率比可控硅的高，但是不注意保护就容易损坏。着重研究过电流故障，并对保护作用的影响进行了分析，进而提出了防止过电流的方法和工作原理。     

基因芯片荧光图象采集与分析

描述了基因芯片荧光图象的光学共聚焦成象,大范围高速扫描与控制,数据采集的原理和方法.并讨论了基因芯片荧光图象的分析算法,即模板定位与阈值分割相结合的半自动算法,并将其计算结果与完全采用人工分割算法的结果进行了比较.     

改进型磁绝缘线振荡器的设计和数值模拟

 综合两种现有磁绝缘线振荡器的优点，对器件进行改进，将双渐变结构、轭流片和阻抗渐变三种增大功率的机制综合考虑，利用二维半全电磁PIC程序进行数值模拟，设计了一种新的改进型磁绝缘线振荡器，当外加电压为550kV，电流为35kA左右时，在L波段获得了6GW的峰值输出功率。     

平行机半在线排序问题研究(Ⅰ)

对半在线平行机排序问题的研究进展作了详细综述和进一步探讨。文章给出半在线排序问题的背景、定义、分类和求解。介绍它们定义和在不同机器环境和目标函数下半在线排序问题分类，以及第一类半在线模型的近似算法的设计及其竞争比分析。     

VLSI Implementation of Forward Error Control Technique for ATM Networks

In asynchronous transfer mode (ATM) networks, fixed length cells of 53 bytes are transmitted. A cell may be discarded during transmission due to buffer overflow or a detection of errors. Cell discarding seriously degrades transmission quality. The quality degradation can be reduced by employing efficient forward error control (FEC) to recover discarded cells. In this paper, we present the design and implementation of decoding equipment for FEC in ATM networks based on a single parity check (SPC) product code using very‐large‐scale integration (VLSI) technology. FEC allows the destination to reconstruct missing data cells by using redundant parity cells that the source adds to each block of data cells. The functionality of the design has been tested using the Model Sim 5.7cXE Simulation Package. The design has been implemented for a 5 ° 5 matrix of data cells in a Virtex‐E XCV 3200E FG1156 device. The simulation and synthesis results show that the decoding function can be completed in 81 clock cycles with an optimum clock of 56.8 MHz. A test bench was written to study the performance of the decoder, and the results are presented.     

一个线性约束优化问题的广义梯度投影法

本文对线性约束优化问题提出了一个新的广义梯度投影法，该算法采用了非精确线性搜索，并在每次迭代运算中结合了广义投影矩阵和变尺度方法的思想确定其搜索方向．在通常的假设条件下，证明了该算法的整体收敛性和超线性收敛速度．