Gauss–Jordan elimination-based image tampering detection and self-recovery

This paper proposes a novel Gauss–Jordan elimination-based image tampering detection and self-recovery scheme, aiming at dealing with the problem of malicious tampering on digital images. To deal with the copy–move tampering which is challenging because the tampered region may contain the watermark information, we propose the Improved Check Bits Generation algorithm during watermark generation, to generate the check bits for tampering detection. Meanwhile, the recovery bits are reconstructed according to the fundamental of Gauss–Jordan Elimination, for purpose of image contents self-recovery. To improve the accuracy of detection and the quality of recovered images, we propose the Morphological Processing-Based Enhancement method and the Edge Extension preprocessing respectively during and after the tampering detection Finally, the Gauss–JordanElimination-Based Self-Recovery method is proposed to recover the damaged content mathematically on basis of the detected results. By employing the unchanged recovery bits which are embedded in the non-tampered region, the failure in recovery caused by the damaged recovery bits can be completely avoided. A large number of experiments have been conducted to show the very good performance of the proposed scheme. The precision, recall, and F1 score are calculated for evaluation of tampering detection, while the PSNR values are calculated for evaluation of image recovery. The comparisons with the state-of-the-art methods show that the proposed scheme shows the superiorities in terms of imperceptibility, security and recovery capability. The experimental result indicates the average PSNR of recovered image is 44.415dB.     

基于优化DA算法的高阶高精度半带滤波器的FPGA实现

随着FPGA技术的稳步提高,FPGA替代其他技术用于实现高速信号处理已经变得切实可行。针对高阶高精度半带滤波器十分消耗FPGA硬件资源的问题,本文提出了采用部分查找表分布式算法及高低位分割处理的改进结构,并通过一个6阶5位低通FIR滤波器进行原形设计,验证了所提出的方法的正确性。仿真结果表明,采用这种方法,在大大减少了FPGA硬件资源的同时,显著提高器件的运算效率。     

测量数据有效数字位数的确定与运算的应用

结合国家计量技术规范和实际应用情况,对测量数据有效数字位数的取位、计算等问题进行了深入的探讨。通过实例,对有效数字的一些概念和问题进行了论述,阐述了能够保证测量精度的测量结果有效数字位数确定、数值修约规则与运算规则等正确方法,解决了有关数据修约与运算所带来的、影响测量结果的问题。     

Quantum packet switching generation using correlated photons in a microring resonator system

We propose a new system of a packet of quantum bits generation using a soliton pulse within a microring resonator. A quantum gate can be formed by using a polarization control unit incorporating into the system. The random signal and idler pairs can be formed within the photon correlation bandwidth, which can be generated, and randomly form the packet quantum bits, i.e. quantum packet switching. Each random code (logic) can be performed by combining the signal and idler of each entangled photon pair via the quantum gate. Results obtained have shown that the packet of quantum logic bits can be generated using the entangled photon pairs generated by the proposed system.     

Quantum bits generation using correlated photons: Fidelity and error corrections

We propose a new system of quantum bits generation using a soliton pulse within a micro ring resonator. A quantum gate can be formed using a polarization control unit incorporating into the system. The random signal and idler pairs can be formed within the photon correlation bandwidth, which can be generated and randomly formed the packet quantum bits, i.e. quantum packet codes. Each random code (logic) can be performed by combining the signal and idler of each entangled photon pair via the quantum gate. Results obtained have shown that the packet of quantum logic bits can be generated using the entangled photon pairs generated by the proposed system. The quantum bits transmission fidelity and error corrections are also described.     

基于多重分形谱的链路层协议帧同步字盲识别

该文针对协议类型未知条件下非等帧长同步字的盲识别问题,提出一种基于多重分形谱的同步字盲识别算法。首先,在定义有偏性的基础上,通过分析比较协议帧、同步字和信息段中0, 1的概率分布,得出协议帧的有偏性小于同步字的结论。然后,利用上述结论并结合多重分形谱具有描述有偏性分布的特点,通过比较删减前后待识别序列多重分形谱宽度的变化实现信息段的有效删减,达到提高同步字浓度的目的。最后,在计算完成删减的序列中固定长度比特串浓度值分布的基础上,实现了同步字的准确识别。仿真试验验证了所提算法的有效性,表明其具有一定的工程应用价值。     

私钥p,q共享低位比特RSA体制的小指数攻击

本文研究了组成RSA模数的两个素数p和q其低位比特相同,RSA公开密钥密码系统的安全性。其结果表明若RSA模数的两个素因子p和q共享低位比特,则当私钥d较小时这样的体制相对于模数不平衡的RSA更易受到攻击。本文的研究结果表明,当组成RSA模数的两个素数p和q仅有少量比特不相同时,使用规模较小的私钥d必须十分慎重。     

WCDMA系统基站阵列接收方案带训练序列的LMS-DRMAT算法

该文针对WCMA系统上行链路帧结构的特征,将Z.Rong(1997)提出的LS-DRMTA改进为利用WCDMA上行链路帧结构中的导频位(pilot bit)作为训练序列的LMS-DRMTA算法。这种新的阵列接收CDMA解调算法相对于LS-DRMTA算法大大降低了基站处理的运算量,提高了算法的实用性,仿真实验还表明该算法比原算法具有更低的误码率。     

双游程编码的无关位填充算法

双游程编码是集成电路测试数据压缩的一种重要方法,可分为无关位填充和游程编码压缩两个步骤.现有文献大都着重在第二步,提出了各种不同的编码压缩算法,但是对于第一步的无关位填充算法都不够重视,损失了一定的潜在压缩率.本文首先分析了无关位填充对于测试数据压缩率的重要性,并提出了一种新颖的双游程编码的无关位填充算法,可以适用于不同的编码方法,从而得到更高的测试数据压缩率.该算法可以与多种双游程编码算法结合使用,对解码器的硬件结构和芯片实现流程没有任何的影响.在ISCAS89的基准电路的实验表明,对于主流的双游程编码算法,结合该无关位填充算法后能提高了6%-9%的测试数据压缩率.     

一个具有改进开关逻辑的12位1MHz采样速率的低功耗逐次逼近型模数转换器

作为数据采集系统中的关键模块,逐次逼近型模数转换器的功耗决定了整个系统的功耗水平。本文给出了一个具有改进开关逻辑的12位1MHz采样速率的低功耗逐次逼近型模数转换器。通过采用所提出的开关逻辑,该逐次逼近型模数转换器的功耗和面积跟采用传统开关逻辑的逐次逼近型模数转换器相比都会有很大的降低,其中开关逻辑的平均功耗大约降低了80%,总的电容面积减小50%。不仅如此,文章还提出了一种简化的数字控制逻辑来降低数字控制电路的功耗和面积。仿真结果表明和传统的数字控制逻辑电路相比,提出的简化数字逻辑的功耗可以减小大约50%。所设计的芯片在标准的0.35微米的CMOS工艺下进行了流片,芯片内核的面积为1.12平方毫米。在-55℃到150℃温度变化范围下,芯片100KHz的输入信号可以测得64.2dB的SNDR。在给定3.3V的电源电压下,芯片的功耗仅为0.72mW。