Extremal Self-Dual [50, 25, 10] Codes with Automorphisms of Order 3 and Quasi-Symmetric 2-(49, 9,6) Designs

Five non-isomorphic quasi-symmetric 2-(49, 9, 6) designs are known. They arise from extremal self-dual [50, 25, 10] codes with a certain weight enumerator. Four of them have an automorphism of order 3 fixing two points. In this paper, it is shown that there are exactly 48 inequivalent extremal self-dual [50, 25, 10] code with this weight enumerator and an automorphism of order 3 fixing two points. 44 new quasi-symmetric 2-(49, 9, 6) designs with an automorphism of order 3 are constructed from these codes.     

一种解决COG图形型液晶显示模块竖条显示的方法

主要研究了COG图形型液晶显示模块的的深竖条显示问题,提出了一个如何提高IC驱动能力的方法。     

Java语言及其虚拟机技术探讨

随着Internet的迅猛发展，Internet编程语言Java愈来愈成为计算机行业的焦点。本文在简述了Java的主要特点后，重点对Java最关键的技术──虚拟机进行了深入的探讨。     

光柱显示技术探讨

本文叙述自动化仪表用光柱显示技术的工作原理及器件结构，重点论述直流等离子体光柱，发光二极管光柱，真空荧光及液晶光柱器件的结构和驱动电路，还展望光柱显示的发展趋势。     

一类三元线性分组码的译码

Ｐｌｅｓｓ［１］证明了三元（１２，６，６）Ｇｏｌａｙ码具有一种双层结构，并据此给出了该码的快速硬判决译码算法。本文推广了Ｇｏｌａｙ码的Ｐｌｅｓｓ结构，给出了由三元（ｎ，ｋ，ｄ）线性分组码构造的三元（３，ｎ＋ｋ，≥ｍｉｎ（ｎ，２ｄ，６））线性分组码，其中包括（１２，６，６）Ｇｏｌａｙ码和（１８，９，６）码，并以三元（１８，９，６）码为例给出了这类码的最大似然软判决译码算法。     

Modular implementation of efficient self-checking checkers for the Berger code

A technique for designing efficient checkers for conventional Berger code is proposed in this paper. The check bits are derived by partitioning the information bits into two blocks, and then using an addition array to sum the number of 1's in each block. The check bit generator circuit uses a specially designed 4-input 1's counter. Two other types of 1's counters having 2 and 3 inputs are also used to realize checkers for variable length information bits. Several variations of 2-bit adder circuits are used to add the number of 1's. The check bit generator circuit uses gates with fan-in of less than or equal to 4 to simplify implementation in CMOS. The technique achieves significant improvement in gate count as well as speed over existing approaches.     

一种可靠多播认证方案及其C语言实现

传统的认证技术对于多播认证并不适用,因为多播认证有它自身的特殊要求。论文介绍了两种针对多播认证特点的解决方案,并结合两种方案的特点阐述了一种改进的适合可靠多播的认证方案,最后给出了C语言的实现。     

Spread Spectrum PN Code Acquisition Using Hybrid Correlator Architectures

A hybrid correlator architecture is described which combines the serial structure of an active correlator with the parallel structure of a matched filter correlator. The mean PN code acquisition time performance of this hybrid serial-parallel correlator structure is analysed. Results are shown which compare the acquisition performance of the serial, parallel, and serial-parallel structures. The results are for a PN code length of 64 code chips and assumes a Gaussian channel with the receiver detection threshold set to obtain a constant false alarm rate. An enhancement to the serial-parallel acquisition algorithm is also described which can increase the acquisition time performance by about 15% for typical operating conditions. Overall the results demonstrate that the hybrid correlator can provide rapid code acquisition with a limited receiver complexity.     

Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test

A system-on-chip (SOC) usually consists of many memory cores with different sizes and functionality, and they typically represent a significant portion of the SOC and therefore dominate its yield. Diagnostics for yield enhancement of the memory cores thus is a very important issue. In this paper we present two data compression techniques that can be used to speed up the transmission of diagnostic data from the embedded RAM built-in self-test (BIST) circuit that has diagnostic support to the external tester. The proposed syndrome-accumulation approach compresses the faulty-cell address and March syndrome to about 28% of the original size on average under the March-17N diagnostic test algorithm. The key component of the compressor is a novel syndrome-accumulation circuit, which can be realized by a content-addressable memory. Experimental results show that the area overhead is about 0.9% for a 1Mb SRAM with 164 faults. A tree-based compression technique for word-oriented memories is also presented. By using a simplified Huffman coding scheme and partitioning each 256-bit Hamming syndrome into fixed-size symbols, the average compression ratio (size of original data to that of compressed data) is about 10, assuming 16-bit symbols. Also, the additional hardware to implement the tree-based compressor is very small. The proposed compression techniques effectively reduce the memory diagnosis time as well as the tester storage requirement.     

The Two-Point Codes with the Designed Distance on a Hermitian Curve in Even Characteristic

In Homma M and Kim SJ [2], the authors considered two-point codes on a Hermitian curve defined over fields of odd characteristic. In this paper, we study the geometry of a Hermitian curve over fields of even characteristic and classify the two-point codes whose minimum distances agree with the designed ones.