Tests of ordered hypotheses in linkage in heredity

The asymptotic null distribution of the likelihood ratio test for two cases of ordered hypotheses in a particular genetic model is considered. A simple iterative process is proposed in order to get the restricted estimates. It is shown that both tests have asymptotically a chi-bar squared distribution and the same size. A simulation study is also conducted in order to compare the usual unrestricted test with the corresponding one of ordered hypotheses. Finally, the results are extended to some special cases.     

专用集成电路CAT技术的进展

本文简单地回顾了提高VLSI测试效率所采用的一些手段,讨论了在ASIC测试问题研究中出现的一些新观点、新方法、新动向,以及所取得的成果。在此基础上,文章阐明了ASIC测试技术的发展方向,并着重论述了可望在未来得到发展的,针对ASIC的功能测试方法。     

A bartlett-type adjustment for the likelihood ratio statistic with an ordered alternative

For testing the equality of normal variances with an increasing alternative, under the null hypothesis the likelihood ratio test statistic is asymptotically distributed as a mixture of chi-squared distributions. In this paper a Bartlett-type adjustment is proposed to improve the approximation of the null distribution of the likelihood ratio test statistic with an ordered alternative.     

Trade-offs in scan path and BIST implementations for RAMs

In this article we propose efficient scan path and BIST schemes for RAMs. Tools for automatic generation of these schemes have been implemented. They reduce the design effort and thus allow the designer to select the more appropriate scheme with respect to various constraints.     

Techniques for estimating test length under random test

When a circuit is tested using random or pseudorandom patterns, it is essential to determine the amount of time (test length) required to test it adequately. We present a methodology for predicting different statistics of random pattern test length. While earlier methods allowed estimation only of upper bounds of test length and only for exhaustive fault coverage, the technique presented here is capable of providing estimates of all statistics of interest (including expected value and variance) for all coverage specifications.Our methodology is based on sampling models developed for fault coverage estimation [1]. Test length is viewed as awaiting time on fault coverage. Based on this relation we derive the distribution of test length as a function of fault coverage. Methods of approximating expected value and variance of test length are presented. Accuracy of these approximations can be controlled by the user. A practical technique for predicting expected test length is developed. This technique is based on clustering faults into equal detectability subsets. A simple and effective algorithm for fault clustering is also presented. The sampling model is applied to each cluster independently and the results are then aggregated to yield test lengths for the whole circuit. Results of experiments with several circuits (both ISCAS '85 benchmarks and other practical circuits) are also provided.This work was done while the author was with the Department of Electrical Engineering, Southern Illinois University, Carbondale, IL 62901.     

Large Sample Properties of Mixture Models with Covariates for Competing Risks

We study the large-sample properties of a class of parametric mixture models with covariates for competing risks. The models allow general distributions for the survival times and incorporate the idea of long-term survivors. Asymptotic results are obtained under a commonly assumed independent censoring mechanism and some modest regularity conditions on the survival distributions. The existence, consistency, and asymptotic normality of maximum likelihood estimators for the parameters of the model are rigorously derived under general sufficient conditions. Specific conditions for particular models can be derived from the general conditions for ready check. In addition, a likelihood-ratio statistic is proposed to test various hypotheses of practical interest, and its asymptotic distribution is provided.     

Mixed-Signal Circuit Classification in a Pseudo-Random Testing Scheme

Pseudo-random testing techniques for mixed-signal circuits offer several advantages compared to explicit time-domain and frequency-domain test methods, especially in a BIST structure. To fully exploit these advantages a suitable choice of the pseudo-random input parameters should be done and an investigation on the accuracy of the circuit response samples needed to reduce the risk of misclassification should be carried out. Here these issues have been addressed for a testing scheme based on the estimation of the impulse response of the device under test (DUT) by means of input-output cross-correlation. Moreover, new acceptance criteria for the DUT are suggested which solve some ambiguity problems arising if the classification of the DUT as good or bad is based on a few samples of the cross-correlation function. Examples of application of the proposed techniques to real cases are also shown in order to assess the impact of the measurement system inaccuracies on the reliability of the test.     

Duane模型在斯特林制冷机研制过程中的应用

介绍一种实用的可靠性增长模型杜安 (Duane)模型 ,并探讨如何运用该模型来分析、指导斯特林制冷机的可靠性增长试验 ,包括试验前的准备、试验数据的处理、曲线的绘制 ,以及如何对增长过程进行估计和监测     

Reducing Average and Peak Test Power Through Scan Chain Modification

Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result in frequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. The transitions embedded in both test stimuli and the responses are handled through scan chain modifications consisting of logic gate insertion between scan cells as well as inversion of capture paths. No performance degradation ensues as these modifications have no impact on functional execution. To reduce average and peak power, we herein propose computationally efficient schemes that identify the location and the type of logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.     

Researches of DC—Problem Under the Model S in which the Numbers of Defective Coins are not Fixed

In this paper,we research general Defective Cion Problem under the model S,i.e,the number d of Defective cions is not fixed. For d=O,1,or 2. we get some good results.