A Platform-Independent Methodology for Performance Estimation of Multimedia Signal Processing Applications

A methodological framework for performance estimation of multimedia signal processing applications on different implementation platforms is presented. The methodology derives a complexity profile which is characteristic for an application, but completely platform-independent. By correlating the complexity profile with platform-specific data, performance estimation results for different platforms are obtained. The methodology is based on a reference software implementation of the targeted application, but is, in constrast to instruction-level profiling-based approaches, fully independent of its optimization degree. The proposed methodology is demonstrated by example of an MPEG-4 Advanced Simple Profile (ASP) video decoder. Performance estimation results are presented for two different platforms, a specialized VLIW media processor and an embedded general-purpose RISC processor, showing a high accuracy of he methodology. The approach can be employed to assist in design decisions in the specification phase of new architectures, in the selection process of a suitable target platform for a multimedia application, or in the optimization stage of a software implementation on a specific platform.Hans-Joachim Stolberg received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1995.From 1995 to 1996, he worked at the NEC Information Technology Research Laboratories, Kawasaki, Japan, on efficient implementation of video compression algorithms. Since 1996, he has been with the Institute of Microelectronic Systems at the University of Hannover as a Research Assistant. During summer 2001, he was a Monbukagakusho Research Fellow at the Tokyo Institute of Technology, Japan. His current research interests include VLSI architectures for video signal processing, performance estimation of multimedia schemes, and profile-guided memory organization approaches for signal processing and multimedia applications.Mladen Bereković received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1995.Since then he has been a Research Assistant with the Institute of Microelectronic Systems of the University of Hannover. His current research interests include VLSI architectures for video signal processing, MPEG-4, System-on-Chip (SOC) designs, and simultaneously multi-threaded (SMT) processor architectures.Peter Pirsch received the Ing. grad. degree from the engineering college in Hannover, Germany, in 1966, and the Dipl.-Ing. and Dr.-Ing. degrees from the University of Hannover, in 1973 and 1979, respectively, all in electrical engineering.From 1966 to 1973 he was employed by Telefunken, Hannover, working in the Television Department. He became a Research Assistant at the Department of Electrical Engineering, University of Hannover, in 1973, a Senior Engineer in 1978. During 1979 to 1981 he was on leave, working in the Visual Communications Research Department, Bell Laboratories, Holmdel, NJ. During 1983 to 1986 he was Department Head for Digital Signal Processing at the SEL Research Center, Stuttgart, Germany. Since 1987 he is Professor in the Department of Electrical and Computer Engineering at the University of Hannover. He served as Vice President Research of the University of Hannover from 1998 to 2002.His present research includes architectures and VLSI implementations for image processing applications, rapid prototyping and design automation for DSP applications. He is the author or coauthor of more than 200 technical papers. He has edited a book on VLSI Implementations for Image Communications (Elsevier 1993) and is author of the book Architectures for Digital Signal Processing (John Wiley 1998).Dr. Pirsch is a member of the IEEE, the German Institute of Information Technology Engineers (ITG) and the German Association of Engineers (VDI). He was recipient of several awards: the NTG paper price award (1982), IEEE Fellow (1997), IEEE Circuits and Systems Golden Jubilee Medal (1999). He was member or chair of several technical program committees of international conferences and organizer of special sessions and preconference courses. He has held several administrative and technical positions with the IEEE Circuits and Systems Society and other professional organizations. Dr. Pirsch currently serves as Vice President Publications of the IEEE Circuits and Systems Society. Since 2000 he is chairman of the Accreditation Commission for Engineering and Informatics of the Accreditation Agency for Study Programs in Engineering, Informatics, Natural Science and Mathematics (ASIIN). Dr. Pirsch is chair of the VDI committee on Engineering Education.     

A 10-Bit,Low Power,Successive Approximation,Digitally Auto-Zeroed CMOS ADC Core for the NASA TRIO Smart Sensor System on a Chip

In spacecraft applications there is a great need for robust analogue to digital converters (ADC) that can withstand the harsh space environment. Commercially available ADCs cannot operate in the space environment due to radiation effects. In this paper we present an ADC that has been developed for the NASA TRIO smart sensor system on a chip (SoC), a versatile low power device specifically designed for spacecraft data acquisition and telemetry of several types of sensors such as temperature, voltage/current transducers, radFETs, etc. It is required for the ADC to operate in excess of 300 Krad total ionizing dose and to be robust to single event upsets. The successive approximation topology was chosen and it was enhanced with a special auto-zeroing technique to compensate for possible lifetime offset errors. Due to the comparator design, a rail-to-rail input capability is achieved, a feature very useful in some type of Vdd ratio metric sensors. It has 10-bit resolution for a reference in the range 0.1 to Vdd + 1 V, and for power supply in the range 2.5 to 5.5 V; the positive reference terminal V_ref+ is settable up to Vdd + 0.5 V and the negative voltage terminal is settable down to GND-0.5 V. The power dissipation is less than 2 mW at 50 Ksamlles/sec. The TRIO chip is used in several NASA spacecraft including CONTOUR, STEREO, MESSENGER, EUROPA, PLUTO, etc.George Kottaras was born in Athens, Greece in 1974. He received the Diploma degree (five years with thesis) in Electrical Engineering from Democritos University of Thrace, Greece in 1996. He is currently pursuing the Ph.D. degree on Scientific Space Instruments and spacecraft avionics at Space Research Laboratory, DUTh. He has specialized in VLSI technologies at JHU/APL for about five years.His research interests include mixed signal analog/digital design, ADCs, design for testability, testing, smart sensors and data acquisition.Nikolaos P. Paschalidis was born is Serres, Greece in 1963. He received the Diploma and Ph.D. degrees in Electrical Engineering from the Democritus University of Thrace (DUTh), Greece, in 1985 and 1992 respectively. He has been in appointment with the Johns Hopkins University, since 1989, where his research specialized in advanced microelectronics, space instrumentation, and space physics.He later joined the Space Department of JHU Applied Physics Laboratory (JHU/APL) Laurel, MD, as a postdoctoral fellow and presently he is Principal Staff. His research interests are in analog and mixed signal microelectronics, microsensors, microsystems and their applications in in-situ and remote sensing spacecraft instruments and avionics. He pioneered in the Advanced Technology Development program of NASA for smaller better faster missions by leading efforts in the circuit level of: amplifiers, comparators, voltage references, ADC and DAC, PLLs, TDCs, SEU and radiation tolerant design, physical design, design for testability, testing and space qualification; in the system on a chip level flight ready chips including: the Time of Flight chip for precise time pickoff and time digitization, Energy chip for radiation energy measurement, the TRIO smart sensor chip for spacecraft data acquisition and control etc; in the instrument and spacecraft level: application of these technologies in particle and plasma spectrometers, laser altimeters, photon/particle imagers, TOF mass spectrometers, X-ray and gamma-ray instruments, spacecraft avionics. Space missions using these technologies include: Cassini, Image, Contour, Messenger, Pluto, Mars missions, etc. Dr. Paschalidis published extensively in microelectronics, space instrumentation, and space physics. He supervises research of graduate students in ECE and Applied Physics. He supervised DUTh graduate students at JHU/APL for many years. He participates as principal investigator and co-investigator in several space programs; he participates in communities with space related activities including: the IEEE Aerospace, Nuclear Sciences, NASA VLSI, IAA, and American Geophysical Union.Emmanuel T. Sarris was bom in Athens, Greece, in 1945. He received the physics degree from the University of Athens in 1967 and the Ph.D. degree in space physics from the University of Iowa, Iowa City, in 1973.He was a Postdoctoral Fellow in the Applied Physics Laboratory, The Johns Hopkins University, Baltimore, MD, from 1974 to 1976. From 1976 to 1977, he was a Research Scientist at the Max-Planck-Institut. He has been a Professor of Electrodynamics, Department of Electrical Engineering, University of Thrace, Greece, and Director of the Laboratory of Electrodynamics and Space Research since 1977. He was the Director of the Institute of Ionospheric and Space Physics, National Observatory of Athens from 1990 to 1996. His research interests include space plasma electrodynamics, design, construction, and testing of space instrumentation, satellite communications, satellite remote sensing. He is coinvestigator in the international space missions: Ulysses, Geotail, Interball, Cluster. He is the author of 270 refereed publications and 300 presentations at international meetings. Dr. Sarris is a member of the COSPAR Council. He was elected Johns Hopkins Scholar Award in 1992 and received the Award for Academic Excellence in 1994.Nikos Stamatopoulos was born in Peloponnisos, Greece in 1969. He received the diploma degree (five years with thesis) of Electrical Engineering from Democritos University of Thrace, Greece in 1994. He is currently pursuing the Ph.D. degree on Scientific Space Instruments at Space Research Laboratory, DUTh. He has specialized in VLSI technologies with emphasis in low noise analog design at JHU/APL for about five years.His main research interests are on Analogue CMOS VLSI design for fast time acquisition.Kostas Karadamoglou was born in Macedonia, Greece, in 1970. He received the diploma degree (five years with thesis) of Electrical Engineering from Democritos University of Thrace, Greece in 1994. He is currently pursuing the Ph.D. degree on Scientific Space Instruments at Space Research Laboratory, DUTh. He has specialized in VLSI technologies with emphasis in high-speed digital design at JHU/APL for about five years.His main research interests are on the design of application specific Time to Digital Converters.Vassilis Paschalidis was born in Serres, Greece in 1964. He received the B.S. degree in Electrical Engineering from the Technological Institute of Kabala, Greece in 1988. He worked n the industry for electronic automation. He has specialized in VLSI technologies at JHU/APL for about five years with emphasis in physical design. His research interests include mixed signal analog/digital VLSI design.     

数字电视时代1550光纤传输技术及应用

详细探讨了数字电视时代数字电视联网的需求及比较,结果表明:1 550光纤传输技术结合光色散补偿技术,在数字电视联网应用中有很强的技术和成本等综合竞争优势。对1 550光纤传输技术在数字电视联网应用中出现的问题以及是否需要色散补偿的问题进行了分析,得出1 550光纤传输技术在数字电视联网应用中色散补偿是很有必要的。最后介绍了1 550数模混合传输网络应用设计实例。     

A New UWB Receiver in the Indoor Multipath Environment

1IntroductionUWBtechnology has receivedincreasing attentionforits broad applicability to short-range wireless communi-cations andradar applications as well .The basic conceptis to transmit , and receive an i mpulse like stream ofverylowpower density for its lowduty cycle and ultra-short duration pulses———typically shorter than a fewnanoseconds .One of the main propagation characteristics of UWBis that signals are spread over a long train of pulses duetothe reflection ,diffractions and sca…     

一种最大长度序列四相码信号脉压性能的研究

介绍了四相编码信号产生及数字脉压实现的方法，分析了采样起始时刻和多普勒频率对脉压结果的影响，比较了两个信号部分叠加时线性脉压和硬限幅脉压的结果。     

10 Gb/s Linear Full-Rate CMOS Phase Detector for Clock Data Recovery Circuit

An improved linear full-rate CMOS 10 Gb/s phase detector is proposed. The improved phase detector overcomes the difficulties in realizing the full-rate operation by adding an I/Q splitter for the input data. Such a topology enlarges the pulse width of output signals to ease the full clock rate operation and the problem of the half period skew in the whole clock data recovery system. The proposed topology is able to provide a good linearity over a wider operating range of input phase offset compared to that of existing designs. The phase detector using the Chartered 0.18 μ m CMOS process is capable of operating up to a 10 GHz clock rate and 10 Gb/s input data for a 1.8 V supply voltage with 31 mW power consumption.     

可编程光学二值双轨逻辑门

基于双轨逻辑,本文提出一种可级联的并行二值逻辑门。所有十六种二值逻辑运算可以采用偏振半波相延编程来实现。也提出了用电光晶体实现实时编程的方法。本文中给出了实验结果。     

A hierarchical test generation methodology for digital circuits

A new hierarchical modeling and test generation technique for digital circuits is presented. First, a high-level circuit model and a bus fault model are introduced—these generalize the classical gate-level circuit model and the single-stuck-line (SSL) fault model. Faults are represented by vectors allowing many faults to be implicitly tested in parallel. This is illustrated in detail for the special case of array circuits using a new high-level representation, called the modified pseudo-sequential model, which allows simultaneous test generation for faults on individual lines of a multiline bus. A test generation algorithm called VPODEM is then developed to generate tests for bus faults in high-level models of arbitrary combinational circuits. VPODEM reduces to standard PODEM if gate-level circuit and fault models are used. This method can be used to generate tests for general circuits in a hierarchical fashion, with both high- and low-level fault types, yielding 100 percent SSL fault coverage with significantly fewer test patterns and less test generation effort than conventional one-level approaches. Experimental results are presented for representative circuits to compare VPODEM to standard PODEM and to random test generation techniques, demonstrating the advantages of the proposed hierarchical approach.     

大功率准连续355nm紫外全固态激光器的研究

报道了一台激光二极管(LD)侧面抽运Nd:YAG腔内倍频与和频准连续355 nm紫外激光器。采用双头Q开关调制的LD侧面抽运Nd:YAG激光器,通过在腔内置入I类非临界相位匹配的三硼酸锂(LBO)晶体进行倍频获得532 nm波长准连续激光,置入两块II类相位匹配的LBO晶体对基频光和倍频光进行两次和频,从而获得了大功率准连续355 nm紫外激光输出。在注入电功率为939.6 W、重复频率为8 kHz时,355 nm激光最大输出功率为15.3 W,脉宽为90 ns,总转换效率为1.63%,其光束质量M2x,M2y分别为4.23和4.56,功率不稳定度为±2.7%。     

一种新型的双幅度定长脉冲间隔调制方式

针对数字脉冲间隔调制(DPIM)存在的问题和性能方面的不足,提出了一种新型的双幅度定长脉冲间隔调制(DAFDPIM)方式,对其调制结构进行了详细阐述,讨论了发射功率、带宽需求、传输容量和差错性能等问题,并与其他几种DPIM的改进方式进行了仿真对比。理论分析和仿真结果表明:这种新型的DAFDPIM方式能实现性能方面较好的平衡,并解决了DPIM符号长度不固定的问题,在无线光通信系统中具有一定的应用前景。