TWO-POINT BOUNDARY VALUE PROBLEM FOR A CLASS OF SECOND-ORDER DIFFERENCE EQUATIONS

In this paper, we apply a critical point theorem and obtain the condition for the existence of three solutions to two-point boundary value problem of a second order nonlinear difference equation.     

系数变号的半线性椭圆方程的正解

本文研究半线性椭圆方程Dirichlet问题-△u=α（x）f(u），x∈Ω， u（x）=0，x∈ЭΩ，正解的存在性，其中Ω为R^n中有界的带光滑边界的区域，α(x)可以变号。     

N指标d维广义Wiener过程象集的m项代数和的几个性质

设珮犠（狋）：犚犖＋ →犚犱是犖指标犱维广义Ｗｉｅｎｅｒ过程，对任意紧集犈１，…，犈犿犚犖＞ ，该文研究了犿项代数和珮犠（犈１）…珮犠（犈犿）的Ｈａｕｓｄｏｒｆｆ维数，Ｐａｃｋｉｎｇ维数和正的Ｌｅｂｅｓｇｕｅ测度及内点的存在性． 其结果包含并推广了布朗单的结果．     

准晶体中八方晶系点群的对称性与矩阵表示

从理论上对准晶体中八方晶系各点群进行了研究.运用八方晶系各点群的极赤投影图,列出了各点群的所有对称操作;填出了固有点群822的群乘表.运用坐标变换和群论在自定义的八方坐标系中,推导出八方晶系点群所有对称操作的矩阵.这32个3×3矩阵的结构是相当简洁的,它们的矩阵元只有5种可能取值:0,±1,±2.其中2是反映八方晶系准晶体所具有的准周期性的特殊无理数.     

欧洲无线DSL的发展现状及市场前景

对欧洲的立法者来说，目前最为关注的课题之一便是如何解决数字鸿沟这一困扰欧洲大陆信息与通信技术整体发展水平的矛盾。向人们提供高速因特网接入服务是消除数字鸿沟的有效手段，而无线数字用户线技术以及其成低、通信质量好、覆盖范围大及灵活性等优势成为宽带接入技术中的佼佼者，并获得很多欧洲国家电信运营商的青睐。     

Thermodynamic modeling of native point defects and dopants of GaN semiconductors

A thermodynamic modeling of GaN was carried out to describe the thermodynamic behavior of native defects, dopants, and carriers (free electrons and holes) in GaN semiconductors. The compound energy model (CEM) was used. An unintentionally doped GaN was taken as an example. Oxygen was introduced into the model as the unintentionally doped impurity, according to the practical experimental phenomena. The energies of component compounds in the model were defined based on the results of the ab initio calculations and adjusted to fit experimental data. The thermodynamic properties of the defects and the oxygen doped were calculated to show the facility of the model.     

Banach空间中渐近正则半群的不动点定理

设X是p一致凸Banach空间,具有弱一致正规结构与非严格的Opial性质.又设C是X的非空凸弱紧子集.在适当的条件下,证明了C上每个渐近正则半群T={T(t):t∈S}都有不动点进一步,在类似的条件下,也讨论了一致凸Banach空间中渐近正则半群的不动点的存在性.     

Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores

This paper introduces a new concept of testability called consecutive testability and proposes a design-for-testability method for making a given SoC consecutively testable based on integer linear programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from test pattern sources (implemented either off-chip or on-chip) consecutively at the speed of system clock. Similarly the test responses are propagated to test response sinks (implemented either off-chip or on-chip) from the core outputs consecutively at the speed of system clock. The propagation of test patterns and responses is achieved by using interconnects and consecutive transparency properties of surrounding cores. All interconnects can be tested in a similar fashion. Therefore, it is possible to test not only logic faults but also timing faults that require consecutive application of test patterns at the speed of system clock since the consecutively testable SoC can achieve consecutive application of any test sequence at the speed of system clock.     

CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing

As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features.This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundray Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation.These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A tool-box environment is provided, in order to automatically generate the needed component to build the chosen SoC test architecture.     

一致Banach空间中非扩张映象的弱收敛定理

设犈是一致凸Ｂａｎａｃｈ空间，满足Ｏｐｉａｌ条件或具有Ｆｒｅｃｈｅｔ可微范数，犆是犈的非空闭凸子集，且犜：犆→犆是非扩张映象．又设对任何初始数据狓１ ∈犆，序列｛狓狀｝由下列修改了的Ｉｓｈｉｋａｗａ迭代程序生成：狓狀＋１ ＝狋狀犜狀（狊狀犜狀狓狀＋ （１－狊狀）狓狀）＋ （１－狋狀）狓狀，　狀≥１， （Ｉ）其中，数列｛狋狀｝与｛狊狀｝满足下列条件（ｉ）和（ｉｉ）之一：（ｉ）狋狀∈ ［犪，犫］且狊狀∈ ［０，犫］；（ｉｉ）狋狀∈ ［犪，１］且狊狀∈ ［犪，犫］，这里，常数犪，犫满足０＜犪≤犫＜１．作者证明了，犜有不动点的充要条件是，｛狓狀｝ 弱收敛且｛‖狓狀－犜狓狀‖｝收敛到０．而且，由此即知，若犜有不动点，则｛狓狀｝弱收敛到犜的一个不动点．