MEMS压力传感器上柔性化凸点制备方法

介绍了一种适用于MEMS压力传感器的低成本、柔性化凸点下金属层(Under Bump Metal,UBM)和凸点(Bump)的制备工艺。其中凸点下金属层分为Ni-P/Cu两层,使用化学镀的方法沉积在Al焊盘表面;凸点通过焊膏印刷回流预制于陶瓷基片上,再通过转移工艺移植到焊盘上。为了检验此套工艺制出的凸点结构是否具有足够的强度,对凸点进行了剪切破坏试验。结果表明,凸点与凸点下金属层、凸点下金属层与Al焊盘均结合牢固,破坏主要发生在焊料凸点内最薄弱的金属间化合物层(Intermetallic Compound,IMC)。     

单行安置的算法

对一j= LSI/VLSI具有积木块的单元，rt卞L给出单f7安置的算法一般来说，给出矩形单元的相对位置后，须从Zw个状态中选出最优解.我们证明在单行安置时可归结为N个状态的问题，得到一种很有效的算法.此算i?;曾用Fortran语言编程并在IBM-PC机上通行，结果令人满意.     

一种时延驱动的VLSI布局方法

时廷特性对于高性能的超大规模集成电路(VLSI)来讲是十分重要的。本文提出了一个新的时延驱动的布局方法。在初始布局中,我们提出了给线网加权的新方法,在迭代改善布局中提出了等位场的概念。实验结果表明:这是一种有效的时延驱动布局方法。     

Evaluating Parallel Simulated Evolution Strategies for VLSI Cell Placement

Simulated Evolution (SimE) is an evolutionary metaheuristic that has produced results comparable to well established stochastic heuristics such as SA, TS and GA, with shorter runtimes. However, for optimization problems with a very large set of elements, such as in VLSI cell placement and routing, runtimes can still be very large and parallelization is an attractive option for reducing runtimes. Compared to other metaheuristics, parallelization of SimE has not been extensively explored. This paper presents a comprehensive set of parallelization approaches for SimE when applied to multiobjective VLSI cell placement problem. Each of these approaches are evaluated with respect to SimE characteristics and the constraints imposed by the problem instance. Conclusions drawn can be extended to parallelization of SimE when applied to other optimization problems.      

用模拟退火算法实现集成电路热布局优化

介绍了一种综合考虑集成电路电学性能指标以及热效应影响的布局优化方法 .在保证传统设计目标 (如芯片面积、连线长度、延迟等 )不被恶化的基础上 ,通过降低或消除芯片上的热点来优化集成电路芯片的温度分布情况 ,进而优化整个电路性能 .并将改进的模拟退火算法应用于集成电路的热布局优化 ,模拟结果表明该方法与传统布局方法相比在保持了较好的延迟与连线长度等设计目标的同时 ,很好地改善了芯片表面的热分配情况     

基于最小自由度优先原则的任意多边形模块布局算法

给出了直角多边形模块自由度的定义和公式,扩展了最小自由度优先原则,使算法能够处理任意直角多边形模块以及有相对约束的模块.实验结果说明该方法在布局效果和效率上都有良好的表现.     

网络延迟聚类的宏观预警的检测点放置

大规模异常事件爆发,使网络可用性受到严重威胁。引发人们对大规模入侵检测系统的研究,其检测效果直接取决于网络检测点选取。大规模网络预警检测点放置问题被转化为网络拓扑有权图聚类问题。针对层次聚类算法面临的初始点选择问题提出基于出度分离初始点选择算法,降低聚类结果对初值的依赖。同时,提出改进双向层次聚类算法DHC,有效降低了结果簇数量。实验证明,此算法整体最优并成功应用于测得的真实全国骨干网络,有效解决了检测点放置问题。     

Layout Driven Selection and Chaining of Partial Scan Flip-Flops

In an era of sub-micron technology, routing is becoming a dominant factor in area, timing, and power consumption. In this paper, we study the problem of selection and chaining of scan flip-flops with the objective of achieving minimum routing area overhead. Most of previous work on partial scan has put emphasis on selecting as few scan flip-flops as possible to break all cycles in S-graph. However, the flip-flops that break more cycles are often the ones that have more fanins and fanouts. The area adjacent to these nodes is often crowded in layout. Such selections will cause layout congestion and increase the number of tracks to chain the scan flip-flops. To take layout information into consideration, we propose a matching-based algorithm to solve the problem. First, an initial placement will be performed before scan flip-flops are selected. Then, iteratively, a matching-based algorithm taking the current layout into account is proposed to select and chain the scan flip-flops. Experimental results show that, on the average, our algorithm can reduce 8.1% area overhead as compared with the previously proposed methods that do not utilize the layout information in flip-flop selection.     

稀疏波长变换网络性能分析与研究

文章对动态业务模型下的稀疏波长变换网络性能进行了分析与研究，对波分复用（WDM）网络中引入波长变换器后的网络性能进行了系统的仿真，分析了波长变换器数量、波长变换器位置、波长变换范围以及路由波长算法等因素对网络性能的影响。     

A survey of surface mount device placement machine optimisation: Machine classification

The optimisation of a printed circuit board assembly line is mainly influenced by the constraints of the surface mount device (SMD) placement machine and the characteristics of the production environment. This paper surveys the characteristics of the various machine technologies and classifies them into five categories (dual-delivery, multi-station, turret-type, multi-head and sequential pick-and-place), based on their specifications and operational methods. Using this classification, we associate the machine technologies with heuristic methods and discuss the scheduling issues of each category of machine. We see the main contribution of this work as providing a classification for SMD placement machines and to survey the heuristics that have been used on different machines. We hope that this will guide other researchers so that they can subsequently use the classification or heuristics, or even design new heuristics that are more appropriate to the machine under consideration.