16×16位高速低功耗并行乘法器的实现

基于0.6μm双阱CMOS工艺模型,实现了一种高速低功耗16×16位并行乘法器。采用传输管逻辑设计电路结构,获得了低功耗的电路性能。采用改进的低功耗、快速Booth编码电路结构和4-2压缩器电路结构,它在2.5V工作电压下,运算时间达到7.18ns,平均功耗(100MHz)为9.45mW。     

VLSI版图验证算法的固化研究

ＶＬＳＩ电路芯片集成度的不断增加，使得设计趋于复杂化，这就对版图验证工具的处理能力与性能提出了进一步的要求，运用特殊的硬件将版图验证的某些算法固化，利用其中内在的并行性来获得处理速度的提高是一类非常有效的方法，本文提出了一种用于在版图验证算法中得到广泛运用的线扫描算法中边排序操作的硬件实现。并且在ＦＰＧＡ上进行了验证，整个系统实现于一块ＰＣ机的扩展卡上，测试的结果表明，对于排序的操作，硬件实现的速     

对偶基上改进CDPD系统RS编解码器的实现

以蜂窝数字分组数据系统(CDPD)中的RS(63，47)码为例，提出了一种建立在伽罗华域(Galois Fields)对偶基乘法器基础上的改进的Reed—Solomon绝解码器。针对CDPD系统的特点，对乘法器、欧几里德算法进行改进，并且应用流水线设计来优化系统，从而提高了编解码速度和性能，节省了硬件资源。该设计不但完全满足CDPD系统的设计要求，而且电路结构便于超大规模集成电路(VLSI)的实现，具有广泛的适用范围。     

一种用于神经计算的竞争电路的设计

作为一种重要的神经元网络的竞争电路，以往的电路实现结构往往有电路复杂度大和相互联接过多的缺点，不利于ＶＬＳＩ实现。在ｒａｉｌ－ｔｏ－ｒａｉｌ放大器结构的基础上，提出了一咱新的ＣＭＯＳ电路实现方法，解决了这些问题。ＨＳＰＩＣＥ的模拟结果证明了设计的正确性。     

A Vlsi Neural Network Processor Based on Hippocampal Model

The hippocampal region of the brain system can be analyzed with the nonlinear system modeling approach. The input-output relationship of the neural units is best represented by the kernel functions of different complexities. The modeling expression of the first and second order kernels are computed in analog current-mode instead of digital data processing in order to fully explore massively parallel processing capability of the neural networks. Two distinct methods are utilized: the table-look-up approach and the model-based approach. The former can achieve high accuracy but consumes large silicon area while the latter saves silicon area and maintains moderately high accuracy. Circuit-level simulation results and experimental data from two test structures are presented.     

Analogue VLSI Leaky Integrate-and-Fire Neurons and Their Use in a Sound Analysis System

Integrate-and-fire neurons are simple model neurons which can handle continuously time-varying signals. We have applied them to problems in real-time analysis of sounds. Two different chips have been built: the first had a fixed network architecture with all synaptic weights identical, and the second is reconfigurable with individually programmable weights. We present results characterising the latter chip, and results from processing real data from the earlier chip. We note that the second chip provides a more general integrate-and-fire neuron implementation.     

基于模块化结构的N位加法器的测试生成

针对单个ｓｔｕｃｋ－ａｔ故障，研究了Ｎ位加法器的测试矢量生成问题，对于行波进位加法器，只需８个测试矢量就可得到１００％的故障覆盖率；对于Ｎ位先行进位加法器，只需Ｎ＾２＋２Ｎ＋３个测试矢量即可得到１００％的故障覆盖率。     

Winner-Takes-All Associative Memory: A Hamming Distance Vector Quantizer

We present a design methodology for mapping neuralyinspired algorithms for vector quantization, into VLSI hardware.We describe the building blocks used: memory cells, current conveyors,and translinear circuits. We use the basic building blocks todesign an associative processor for bit-pattern classification;a high-density memory based neuromorphic processor. Operatingin parallel, the single chip system determines the closest match,based on the Hamming distance, between an input bit pattern andmultiple stored bit templates; ties are broken arbitrarily. Energyefficient processing is achieved through a precision-on-demandarchitecture. Scalable storage and processing is achieved througha compact six transistor static RAM cell/ALU circuit. The singlechip system is programmable for template sets of up to 124 bitsper template and can store up to 116 templates (total storagecapacity of 14 Kbits). An additional 604 bits of auxiliary storageis used for pipelining and fault tolerance re-configuration capability.A fully functional 6.8 mm by 6.9 mmchip has been fabricated in a standard single–poly, double–metal2.0µmn–well CMOS process.     

基于边界元法的二维VLSI版图电容提取

提出了一种用边界元法计算ＶＬＳＩ版图电容的方法，通过求解二维拉普拉斯方程，直接得到版图中各种类型的电容的值。该方法提取数据准确简单，占用内存少，计算效率高，且有较高的精度。用该方法对几种典型的ＶＬＳＩ版图电容进行提取，均取得较好的结果。     

An algorithm ofk-line location for BBL in LSI/VLSI

In this paper, aK-line location algorithm for building block cells in LSI/VLSI is presented. When the relative positions of rectangular cells are given, there are 2 states according to the two orientations of a cell. It is proved that to find the optimum solution from the 2^N states can be reduced to calculate theN states inK-line algorithm. So the algorithm is shown very effective and can be used with association for cluster method in BBL placement. Under certain conditions, this method can also be used to pesudo BBL placement directly.