小波图像编码的VLSI实现

设计了一种模块化的二维离散小波变换(2-D DWT)的VLSI结构.该结构可以实时完成小波变换,且很容易扩展.针对零树编码硬件实现方面的不足,利用一种简单的顺序扫描方式和两个标志阵列,设计了一种适合硬件实现的快速零树编码算法(FZIC)和FZIC硬件实现的VLSI结构,编写了2-D DWT和FZIC硬件结构的Veri log HDL模型,并进行了仿真和逻辑综合.结合2-D DWT和FZIC,实现了小波图像编码系统 ,并用ALTERA CPLD成功进行了验证.     

Fault-tolerance in balanced sorting networks

Much research has been done on sorting networks but there are very few results concerning their robustness. Our starting point is the balanced sorting network introduced by Dowd et al. and its single-block robust design of Rudolph obtained at the cost of some redundancy and two permuters external to the network. In this article we introduce a new implementation which is more robust than Rudolph's network and needs no redundancy or external permuters. We also consider a class of single-stage designs with redundancy and compare the characteristics of networks discussed.     

分布式安全组播体系结构的实现

随着因特网不断商业化和用户数量的急剧增加，组播通信中的安全问题受到研究人员的日益关注。许多研究机构提出了解决这些安全问题的体系结构。文章通过分析组播的安全问题和安全服务，给出了设计体系结构中需要注意的问题。在分析这些体系结构的基础上，提出了具有安全策略的DSMA(Dist Iibuted Secure Mumcast Architecture)体系结构，它对Iolus单点故障进行了解决。最后给出了DSMA的实现方案。     

Deterministic one-dimensional cellular automata

A formal treatment of some of the properties of deterministic, rule 150, elementary one-dimensional cellular automata (CA) with null boundary conditions is presented. The general form of the characteristic polynomial of the CA global rule transition matrix is obtained. Mathematical relationships between the CA register lengths and the order of the corresponding group or semigroup structures are derived.     

High performance set associative translation lookaside buffers for low power microprocessors

A fast low power four-way set-associative translation lookaside buffer (TLB) is proposed. The proposed TLB allows single clock phase accesses at clock frequencies above 1 GHz. Comparisons to a conventional fully associative CAM tagged TLB, which is the type most commonly used in embedded processors, with the same number of entries on a 65 nm low standby power process show that the proposed design has 28% lower delay and up to 50% lower energy delay product. Unlike previous set-associative TLBs, which replicate the TLB to support multiple page sizes, multiple page sizes are supported on a way-by-way basis. Alternative conventional CAM tagged and set-associative TLBs are investigated with regard to access latency, power dissipation and hit rates.     

Architecture Concepts for Multimedia Signal Processing

Architectural concepts are presented aimed at future multimedia processing schemes. Starting from an analysis of current and future multimedia applications, specific computational requirements are derived. It will be shown that multimedia applications benefit from an exhaustive and flexible exploitation of parallelism. Three architectural concepts—reconfigurable computing, simultaneous multithreading, and associative controlling—are presented, and their potential to increase further the performance on future multimedia applications is investigated.     

EPS系统的QoS机制

为了适应未来10年移动通信技术的发展，给用户不断增强的数据业务需求提供更好支持，3GPP组织启动了长期演进计划（LTE）与系统框架演进（SAE）研究项目。针对未来数据业务具有高速、突发性的特征，演进的分组系统（EPS）对服务质量（QoS）机制进行了诸多改进与增强，通过引入默认承载、聚合资源调度等概念，真正实现了用户的“永远在线”，提高了业务的数据速率，进而最终提升了用户体验。同时，针对未来UTRAN与E-UTRAN网络之间的互操作场景，设计了EPS的QoS等级标识（QCI）参数与通用移动通信系统（UMTS）QoS参数之间的合理映射。     

基于行的实时、二维提升整数小波变换VLSI结构

提出一种基于行的实时、二维提升整数小波变换的VLSI结构。该结构包括行变换器、列变换器、中间缓存器以及输出控制单元。利用中间缓存器暂存行变换的中间结果,由输出控制单元按优先级从高到低的顺序依次输出各级小波系数。由于在硬件实现中采用基于行的提升变换结构,从而水平和垂直方向上的变换能并行处理。与现有结构相比,该结构具有并行度高、存储量低的特点,并且能够在一幅图像逐行扫描的时间间隔内完成整幅图像的多级小波变换。     

VLSI电源网络近似电路模型研究

针对基于底层规划的电源网络分析、优化需求,提出了一种电源网络近似电路模型.根据电源网络结构特点,对其进行层次划分,并充分考虑标准单元吸纳电流的统计分布特性,建立各组成元件的电路模型.在此基础上,利用诺顿等效原理对其进行简化.实验表明,基于近似电路模型的电源网络分析结果比悲观分析要小38.75%(最差电压降)和36.04%(中心节点电压降),分析结果更为可信.