深亚微米VLSI物理设计中天线效应的预防及修复

深亚微米超大规模集成电路(VLSI)中金属互连线的天线效应(PAE)将会严重影响芯片物理设计的结果,甚至造成设计的失败。因此详细分析了天线效应的产生、危害和计算方法,重点讨论了深亚微米VLSI芯片物理设计中的PAE预防和修复方法,并且针对面积和时序要求苛刻的复杂芯片设计提出了优化的迭代流程。上述方法和流程成功应用于本研究室协作承担的"风芯Ⅱ号"H.264/AVC-AVS视频解码SoC芯片的后端物理设计过程中,极大地提高了天线效应的预防和修复效率,消除了版图中全部潜在高危PAE问题且节省了18.18%的迭代次数,节约了17.39%的芯片管芯面积,确保并实现了芯片流片的一次成功。     

基于MDA的工作流门户整体风格的配置

针对不同的企业对业务过程管理有不同需求的问题，提出了可配置整体风格的业务过程管理门户。通过分析门户的组成来讲述门户整体风格配置所涉及的各个方面，并根据MDA（模型驱动框架）的思想给出具体的实现方案和步骤。     

Modular analysis and design of log-domain circuits based on LIN↔ELIN transformations

We systematized and developed some procedures for the modular design of externally-linear internally nonlinear (ELIN) circuits resulting in a general LIN↔ELIN transformation procedure. This one was also extended to analysis of these types of circuits. The procedure is exemplified on log-domain circuits. In the design one starts with the linear block diagram (LIN) described by transfer functions and one substitutes directly each linear building block by a corresponding nonlinear one. The parameters of each nonlinear component depend on the given parameters of its linear correspondent. Input F ⁻¹ and output F blocks are added. In the analysis one identifies the nonlinear basic circuit components and each of them is substituted by its corresponding linear building block. Input and output F ⁻¹-F cells are removed. The ideal transfer function can be calculated on the linear block diagram now. The LIN↔ELIN transformations make a direct connection between equivalent linear and ELIN circuits, simplify their design and analysis procedures and permit the development of CAD procedures.     

A two-level reconfigurable architecture for digital signal processing

This paper describes a novel reconfigurable architecture for digital signal processing (DSP). This architecture consists of a two-level array of cells and interconnections. On the upper level, fundamental DSP operations such as multiplication and addition are mapped onto blocks of 4-bit cells. On the lower level, each cell uses a 4 × 4 matrix of smaller “elements” to perform the necessary computations. Cells also contain pipeline latches for increased throughput. The architecture features a simple VLSI implementation that combines the flexibility of memory elements with the speed of DOMINO logic. Initial prototypes have been fabricated using a modest 0.5-μm CMOS technology. Circuit simulations of the cell in 0.25-μm technology indicate that the design achieves a clock frequency of 200 MHz.     

椭圆曲线密码处理器的高效VLSI设计与实现

采用复合武硬件设计方法，通过数学公式推导和电路结构设计，完成了一款GF（2m）域椭圆曲线密码处理器的高效VLSI实现。以低成本为目标，对算术逻辑模块的乘法、约减、平方、求逆，以及控制电路模块都进行了优化设计。按照椭圆曲线密码的不同运算层次，设计了不同层次的控制电路。该处理器综合在中芯国际SMIC0．18μm标准工艺库上．比相关研究的芯片面积节省48％，同时保证了很快的速度。     

后3G时代LTE异军突起

介绍了下一代无线网络LTE(Long Term Evolution,长期演进)的背景和发展状况.分析了LTE的技术特征,阐述了LTE网络结构与核心技术,并通过与WiFi(WirelessFidelity)及WiMAX(World wide Inter operability for Microwave Access)的各项性能作比较,着重分析了LTE的技术优势.最后,指出了LTE在个人通信市场所面临的应用前景与挑战.     

神经网络在非线性规划中的应用

本文对蔡少棠[1 ] ,[2 ] 等提出的非线性规划神经网络作了改进 ,使得该神经网络适合于通用VLSI技术实现 .     

High-level parameterizable area estimation modeling for ASIC designs

Architectural design space exploration and early area budgeting for ASIC and IP block development require accurate high level gate count estimation methods without requiring the hardware being fully specified. The proposed method uses hierarchical and parameterizable models requiring minimal amount of information about the implementation technology to meet this goal. The modeling process flow is to: (1) create a block diagram of the design, (2) create a model for each block, and (3) sum up estimates of all sub-blocks by supplying the correct parameters to each sub-model. We discuss the model creation for a few parameterized library blocks as well as three communication blocks and a processor core from real IC projects ranging from 22 to 250 kgates. The average relative estimation error of the proposed method for the library blocks is 3.2% and for the real world examples 4.0%. The best application of this method is early in the design phase when different implementation architectures are compared.     

小波图像编码的VLSI实现

设计了一种模块化的二维离散小波变换(2-D DWT)的VLSI结构.该结构可以实时完成小波变换,且很容易扩展.针对零树编码硬件实现方面的不足,利用一种简单的顺序扫描方式和两个标志阵列,设计了一种适合硬件实现的快速零树编码算法(FZIC)和FZIC硬件实现的VLSI结构,编写了2-D DWT和FZIC硬件结构的Veri log HDL模型,并进行了仿真和逻辑综合.结合2-D DWT和FZIC,实现了小波图像编码系统 ,并用ALTERA CPLD成功进行了验证.     

Fault-tolerance in balanced sorting networks

Much research has been done on sorting networks but there are very few results concerning their robustness. Our starting point is the balanced sorting network introduced by Dowd et al. and its single-block robust design of Rudolph obtained at the cost of some redundancy and two permuters external to the network. In this article we introduce a new implementation which is more robust than Rudolph's network and needs no redundancy or external permuters. We also consider a class of single-stage designs with redundancy and compare the characteristics of networks discussed.