教育信息化云服务平台的设计与实现

随着云计算技术的迅速发展,教育云也越来越成为教育信息化的研究热点.云计算与教育的结合,对于建立开放灵活的教育信息化服务平台,实现资源共享有着重要的意义.本研究分析了教育云的发展现状,设计了教育信息化云服务平台的技术架构并且基于该平台设计搜索、学习、资源、管理等多种云服务.基于该架构开发了面向终身教育的“随身学”云学习系统,并对其进行了易用性测试.     

双π型RF EMIF的一种薄膜集成制造方法

基于双兀型电磁干扰滤波器(EMIF)的电路结构,借鉴了集成电路超微细加工技术,提出了与等平面超大规模集成电路工艺完全兼容的双兀型EMIF电路的薄膜集成制造方法.该方法可用于制作满足未来电子系统的高频化、小型化、轻型化和片式化信号处理EMIF电路的应用需求,改善双兀型EMIF电路的信号处理性能,还可将其与VLSI一起片上集成.     

A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic

In this paper, we have analyzed the register complexity of direct-form and transpose-form structures of FIR filter and explored the possibility of register reuse. We find that direct-form structure involves significantly less registers than the transpose-form structure, and it allows register reuse in parallel implementation. We analyze further the LUT consumption and other resources of DA-based parallel FIR filter structures, and find that the input delay unit, coefficient storage unit and partial product generation unit are also shared besides LUT words when multiple filter outputs are computed in parallel. Based on these finding, we propose a design approach, and used that to derive a DA-based architecture for reconfigurable block-based FIR filter, which is scalable for larger block-sizes and higher filter-lengths. Interestingly, the number of registers of the proposed structure does not increase proportionately with the block-size. This is a major advantage for area-delay and energy efficient high-throughput implementation of reconfigurable FIR filters of higher block-sizes. Theoretical comparison shows that the proposed structure for block-size 8 and filter-length 64 involves 60% more flip-flops, 6.2 times more adders, 3.5 times more AND-OR gates, and offers 8 times higher throughput. ASIC synthesis result shows that the proposed structure for block-size 8 and filter-length 64 involves 1.8 times less area-delay product (ADP) and energy per sample (EPS) than the existing design, and it can support 8 times higher throughput. The proposed structure for block sizes 4 and 8, respectively, consumes 38% and 50% less power than the exiting structure for the same throughput rates on average for different supply voltages.     

A heuristic for constructing a rectilinear Steiner tree by reusing routing resources over obstacles

The obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) problem is a hot topic in very-large-scale integration physical design. In practice, most of the obstacles occupy the device layer and certain lower metal layers. Therefore, we can place wires on top of the obstacles. To maximize routing resources over obstacles, we propose a heuristic for constructing a rectilinear Steiner tree with slew constraints. Our algorithm adopts an extended rectilinear full Steiner tree grid as the routing graph. We mark two types of Steiner point candidates, which are used for constructing Steiner trees and refining solutions. A shortest path heuristic variant is designed for constructing Steiner trees and it takes into account slew constraint by inhibiting growth. Furthermore, we use a pre-computed strategy to avoid calculating slew rate repeatedly. Experimental results show that our algorithm maximizes routing resources over obstacles and saves routing resources outside obstacles. Compared with the conventional OARSMT algorithm, our algorithm reduces the wire length outside obstacles by as much as 18.74% and total wire length by as much as 6.03%. Our algorithm improves the latest related algorithm by approximately 2% in terms of wire length within a reasonable running time. Additionally, calculating the slew rate only accounts for approximately 15% of the total runing time.     

Synthesis of Dual Mode Logic

In recent years, the major focus of VLSI design has shifted from high-speed to low-power consumption. While standard CMOS-based digital design provides substantial flexibility during pre-silicon design phases, the characteristics of the gates are set by fabrication variations and environmental conditions and cannot easily be changed at runtime. The recently proposed Dual Mode Logic (DML) family provides a novel approach to provide this capability by introducing two configurable operating modes, static and dynamic, that enable fine-grained control of the power-performance tradeoff of a logic path. However, the introduction of a new topology requires the development of both a design methodology and techniques for integration in a robust design automation flow. Standard synthesis tools do not support dynamic gates, and in particular, dual-characteristic gates. Therefore, until now, DML has been limited to small, custom-made blocks and components. In this paper, we present a novel approach for the integration of DML into standard electronic design automation tools, as part of the standard digital design flow. The development of this approach and the accompanying design methodology enables DML to be used in larger designs, such as state-of-the-art, high-speed and/or low-power SoCs. We demonstrate the employment of the proposed approach in order to benefit from DML properties, and reduce the power consumption, while simultaneously improving the operating frequency of a number of test designs.     

基于G/S模式的空间信息云服务架构研究

针对多系统间的数据交换、共享问题,尤其在大数据时代,海量的数据增长给数据的管理带来的挑战,提出了一种基于G/S(General-Browser/ Service-Cloud,G/S)模式的空间信息云服务架构——面向数据的架构(Data Oriented Architecture,DOA)。以数据为核心,以数据标识为主线,通过数据注册中心和数据交换规范XXML(Specific Industry Markup Language),对海量异构数据进行存储、计算和管理,实现多系统间的数据共享、访问和协同。通过在地质灾害监测预警方面的应用,证明了该架构作为信息技术的系统构建方法在大数据时代独特的优势。     

DES加密算法的VLSI实现方法

简述了DES加密算法的发展历史和核心思想,并给出了一种VLSI实现方法.并且在数据通道中采用了流水线结构,这样的结构比软件实现有着更好的加密性能.文中着重介绍了DES算法中的S-Box,替换和迭代过程.     

面向服务架构汽车软件开发方法和实践

面向服务架构(SOA)是智能网联汽车软件的主要设计模式之一,为有效设计SOA汽车软件,发挥SOA软件设计模式的优势,提出了一种SOA汽车软件分层模型,描述了基于该模型的两种SOA汽车软件开发方法,并介绍了相应的开发实践,最后描述了所开发的SOA汽车软件在域控制器上的部署.     

国防信息基础设施的建设与管理

讨论了国防信息基础设施的概念,分析了美军国防信息基础设施的发展状况、实施方法、主要途径,提出了发展我军信息基础设施的技术途径和措施建议.     

基于多端口存储器互连结构的多处理器系统芯片设计

多处理器系统芯片设计的关键问题之一是微处理器之间的互连结构.在总线互连结构和开关互连结构之后,提出了基于多端口存储器的第3种互连结构.利用VHDL进行了多时钟多端口存储器设计,并利用EDA工具进行了片上系统芯片的多微处理器数据通讯的功能仿真.分析了基于总线、基于开关、基于多端口存储器的3种互连结构的特点.研究表明基于多端口存储器的互连结构具有异步数据传输,数据缓冲功能;具有数据传输延时小,多微处理器系统芯片的拓扑阵列规模可扩展的优点.