Ad Hoc网络技术研究进展

AdHoc网络现在是非常有吸引力的研究方向。本文介绍了Ad Hoc网络的定义、特点、体系结构、信道接入协议，最后分析了Ad Hoc网络面临的问题。希望本文能为进行AdHoc网络技术研究的人们提供一定的方便。     

MPEG-4视频编码器象素压缩模块的VLSI结构设计

文章设计了一种基于MPEG-4的视频压缩编码器中象素压缩模块的VLSI结构。该设计采用分布算式结构——NEDA作为DCT变换的核心技术；应用基于LUT表结构使量化／反量化模块的设计简洁明了；同时对AC／DC预测模块还应用了新的存储策略，大大降低了FPGA中宝贵的存储空间。在满足处理速度和精度的要求下，利用了较少的晶体管数目和简洁的结构实现了象素压缩模块。     

FPGA Implementation of a Pipelined On-Line Backpropagation

The paper describes the implementation of a systolic array for a multilayer perceptron with a hardware-friendly learning algorithm. A pipelined modification of the on-line backpropagation algorithm is shown and explained. It better exploits the parallelism because both the forward and backward phases can be performed simultaneously. The neural network performance for the proposed modification is discussed and compared with the standard so-called on-line backpropagation algorithm in typical databases and with the various precisions required. Although the preliminary results are positive, subsequent theoretical analysis and further experiments with different training sets will be necessary. For this reason our VLSI systolic architecture—together with the combination of FPGA reconfiguration properties and a design flow based on generic VHDL—can create a reusable, flexible, and fast method of designing a complete ANN on a single FPGA and can permit very fast hardware verifications for our trials of the Pipeline On-line Backpropagation algorithm and the standard algorithms.     

WCDMA QoS机制解析

阐述了WCDM AQoS机制的结构体系、业务类别和相关流程；介绍了中兴通讯QoS控制设计思想。     

基于CORDIC算法并行FFT设计与硬件实现

讨论了复杂128点FFT处理器的并行和旋转结构。VLSI实现FFT适用于超高速数据处理。随着新的VLSI技术的发展，高速处理和低功耗设计成为现实。使用CORDIC旋转处理器可以优化面积和速度的设计，在不降低数据处理速度的基础上，这种FFT仅仅使用了5．3万等效逻辑门。     

Neuromorphic Synapses for Artificial Dendrites

We describe neuromorphic, variable-weight synapses onartificial dendrites that facilitate experimentation with correlativeadaptation rules. Attention is focused on those aspects of biologicalsynaptic function that could affect a neuromorphic network'scomputational power and adaptive capability. These include sublinearsummation, quantal synaptic noise, and independent adaptationof adjacent synapses. The diffusive nature of artificial dendritesadds considerable flexibility to the design of fast synapsesby allowing conductances to be enabled for short or for variablelengths of time. We present two complementary synapse designs:the shared conductance array and the self-timed synapse. Bothsynapse circuits behave as conductances to mimic biological synapsesand thus enable sublinear summation. The former achieves weightvariation by selecting different conductances from an on-chiparray, and the latter by modulating the length of time a constantconductance remains activated. Both work with our interchip communicationsystem, virtual wires. For the present purpose of comparing variousadaptation mechanisms in software, synaptic weights are storedoff chip. This simplifies the addition of quantal weight noiseand allows connections from different sources to the same dendriticcompartment to have independent weights.     

应用于VLSI的PSSWS-LDD MOSFET优化工艺研究

提出实现VLSI的PSSWS(Poly Silicon Side Wall Spacer)—LDD(Lightly DopedDrain)结构,研究了它的形成工艺,获得多晶侧壁形成的优化工艺条件,制作出亚微米有效沟道长度的LDD NMOSFET。在器件性能研究和计算机模拟的基础上,得到PSSWS—LDDMOSFET的优化工艺实现条件;此条件下实现的有效沟道长为0.8μm的PSSWS—LDDNMOSFET,源漏击穿电压达20V,常规器件的小于16V;衬底电流较常规器件的减小约二个数量级。利用此优化条件,研制出高性能的1μm沟道长度的CMOS CD4007电路,2μm沟道长的21级CMOS环振,LSI CMOS 2.5μm沟道长度的门阵列电路GA 300 5SD。结果表明:PSSWS—LDD MOSFET性能衰退小,速度快,可靠性高,适用于VLSI的制造。     

Analog VLSI Circuits for Competitive Learning Networks

An investigation is made concerning implementations of competitive learning algorithms in analog VLSI circuits and systems. Analog and low power digital circuits for competitive learning are currently important for their applications in computationally-efficient speech and image compression by vector quantization, as required for example in portable multi-media terminals. A summary of competitive learning models is presented to indicate the type of VLSI computations required, and the effects of weight quantization are discussed. Analog circuit representations of computational primitives for learning and evaluation of distortion metrics are discussed. The present state of VLSI implementations of hard and soft competitive learning algorithms are described, as well as those for topological feature maps. Tolerance of learning algorithms to observed analog circuit properties is reported. New results are also presented from simulations of frequency-sensitive and soft competitive learning concerning sensitivity of these algorithms to precision in VLSI learning computations. Applications of these learning algorithms to unsupervised feature extraction and to vector quantization of speech and images are also described.     

薄膜全耗尽SOI短沟道MOSFET准二维电流模型

本文在分析薄膜全耗尽SOI器件特殊物理效应的基础上,建立了可细致处理饱和区工作特性的准二维电流模型。该模型包括了场效应载流子迁移率、速度饱和以及短沟道效应等物理效应,可以描述薄膜全耗尽SOI器件所特有的膜厚效应、正背栅耦合(背栅效应)等对器件特性的影响,并且保证了电流、电导及其导数在饱和点的连续性。将模型模拟计算结果与二维器件数值模拟结果进行了对比,在整个工作区域(不考虑载流子碰撞离化的情况下)二者吻合得很好。     

嵌入式计算机PC-104在飞行控制系统中的应用

文章中给出了嵌入式计算机PC-104在某小型飞行器飞行控制系统中的应用。详细介绍了系统体系结构及各部分功能,提出几个技术问题及解决措施,并给出软件模块功能、流程图以及各模块之间的调度关系和实时性处理方法。