用边界元法提取VLSI版图电阻

介绍了ＶＬＳＩ版图验证中电阻提取的基本原理和主要方法，给出了一种新颖的基于边界元法的电阻提取算法。该算法采用变节点单元，较好地解决了实际问题中经常出现的角点问题。通过应用该算法对几个实例进行提取，证明使用本文的算法不仅在精度上而且在占用ＣＰＵ时间上都取得了令人满意的效果     

行为级DSP算法描述的阵列处理器综合方法研究

本文提出了针对递归DSP算法的高层次系统综合流程,并以脉动(systolic)式处理器阵列结构实现.从DSP算法的FDDL行为级描述开始,经由编译及划分,产生数据相关流图(Data Dependency Graph),然后实现对算法流图的空间映射及时域规划,得到算法的信号流图(Signal Flow Graph),经时序重构,生成脉动阵列,最后实现对处理器单元的数据路径综合及控制器综合,并对处理器单元定位,本文同时提出了各设计阶段的算法策略及优化策略,并给出综合结果。     

CADRE: An Asynchronous Embedded DSP for Mobile Phone Applications

Asynchronous design techniques have a number of compelling features that make them suited for complex system on chip designs. However, it is necessary to develop practical and efficient design techniques to overcome the present shortage of commercial design tools. This paper describes the development of CADRE (Configurable Asynchronous DSP for Reduced Energy), a 750K transistor, high performance, low-power digital signal processor IP block intended for digital mobile phone chipsets. A short time period was available for the project, and so a methodology was developed that allowed high-level simulation of the design at the earliest possible stage within the conventional schematic entry environment and simulation tools used for later circuit-level performance and power consumption assessment. Initial modeling was based on C behavioral models of the various data and control components, with the many asynchronous control circuits required automatically generated from their specifications. This has enabled design options to be explored and unusual features of the design, such as the Register Bank which is designed to exploit data access patterns, are presented along with the power and performance results of the processor as a whole.     

超大规模集成电路中互连结构的逻辑模型

本文首次提出一种新观点，超大规模集成电路中互连结构的等效模型应具有层次性，对于底层的电路设计，应将互加看作一种具有分布参数的多端口网络，而对于高层次的模块设计，则应将互连看作一种逻辑元件，基于这种观点，本文提出了一种表格型的逻辑模型，它可以将互连产生的三种主要负效应：串扰、延迟和信号变形人武部考虑在内。     

Ultra-trace analysis of U,Th, Ca and selected heavy metals in high purity refractory metals with isotope dilution mass spectrometry

A method for the determination of trace impurities (U, Th, Ca, Fe, Cr, Ni, Cu, and Cd) in the refractory metals molybdenum and tungsten with isotope dilution mass Spectrometry (IDMS) has been developed. This method enables determinations of uranium and thorium down to the lowest pg/g level with high precision and accuracy. Selective chromatographic, extractive and electrolytic methods for the trace-matrix separation were combined with positive thermal ionization mass spectrometry. Different samples of high purity (4N) and of ultra high purity (UHP) materials for advanced technologies were analysed. The detection limits reached are (in ng/g): U 0.006, Th 0.008, Ca 10, Fe 19, Cr 0.5, Ni 0.6, Cu 2.7, and Cd 0.12. A comparison of results with other sensitive analytical methods (ICP-MS, GDMS, SIMS) makes obvious the urgent necessity of a reliable calibration method like IDMS because the analytical results obtained by the other methods often spread over a wide range.     

A CAM-based keyword match processor architecture

This paper demonstrates a keyword match processor capable of performing fast dictionary search with approximate match capability. Using a content addressable memory with processor element cells, the processor can process arbitrary sized keywords and match input text streams in a single clock cycle. We present an architecture that allows priority detection of multiple keyword matches on single input strings. The processor is capable of determining approximate match and providing distance information as well. A 64-word design has been developed using 19,000 transistors and it could be expanded to larger sizes easily. Using a modest 0.5 μm process, we are achieving cycle times of 10 ns and the design will scale to smaller feature sizes.     

一种基于遗传算法的VDSM IC电源网格动态IR-drop分析新方法

提出了一种用于超深亚微米集成电路电源网格IR-drop验证的新方法.该方法以遗传算法为基础,与已有的分析方法相比,该方法兼具静态IR-drop分析法和动态IR-drop分析法的优点,适用于包含大型组合模块的超大规模集成电路,可主动寻找电路中最大IR-drop.通过对ISCAS85电路实现的验证,发现了静态分析法不能发现的芯片边缘IR-drop问题.实验结果验证了该方法的正确性与有效性.     

VLSI集成电路参数成品率及优化研究进展

VLSI的参数成品率是与制造成本和电路特性紧密相关的一个重要因素,随着集成电路(IC)进入超深亚微米发展阶段,芯片工作速度不断增加,集成度和复杂度提高,而工艺容差减小的速度跟不上这种变化,因此参数成品率的研究越来越重要.本文系统地讨论了参数成品率的模型和设计技术研究进展,分析不同技术的特点和局限性.最后提出了超深亚微米(VDSM)阶段参数成品率设计和成品率增强面临的主要问题及发展方向.     

A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic

In this paper, we have analyzed the register complexity of direct-form and transpose-form structures of FIR filter and explored the possibility of register reuse. We find that direct-form structure involves significantly less registers than the transpose-form structure, and it allows register reuse in parallel implementation. We analyze further the LUT consumption and other resources of DA-based parallel FIR filter structures, and find that the input delay unit, coefficient storage unit and partial product generation unit are also shared besides LUT words when multiple filter outputs are computed in parallel. Based on these finding, we propose a design approach, and used that to derive a DA-based architecture for reconfigurable block-based FIR filter, which is scalable for larger block-sizes and higher filter-lengths. Interestingly, the number of registers of the proposed structure does not increase proportionately with the block-size. This is a major advantage for area-delay and energy efficient high-throughput implementation of reconfigurable FIR filters of higher block-sizes. Theoretical comparison shows that the proposed structure for block-size 8 and filter-length 64 involves 60% more flip-flops, 6.2 times more adders, 3.5 times more AND-OR gates, and offers 8 times higher throughput. ASIC synthesis result shows that the proposed structure for block-size 8 and filter-length 64 involves 1.8 times less area-delay product (ADP) and energy per sample (EPS) than the existing design, and it can support 8 times higher throughput. The proposed structure for block sizes 4 and 8, respectively, consumes 38% and 50% less power than the exiting structure for the same throughput rates on average for different supply voltages.     

A heuristic for constructing a rectilinear Steiner tree by reusing routing resources over obstacles

The obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) problem is a hot topic in very-large-scale integration physical design. In practice, most of the obstacles occupy the device layer and certain lower metal layers. Therefore, we can place wires on top of the obstacles. To maximize routing resources over obstacles, we propose a heuristic for constructing a rectilinear Steiner tree with slew constraints. Our algorithm adopts an extended rectilinear full Steiner tree grid as the routing graph. We mark two types of Steiner point candidates, which are used for constructing Steiner trees and refining solutions. A shortest path heuristic variant is designed for constructing Steiner trees and it takes into account slew constraint by inhibiting growth. Furthermore, we use a pre-computed strategy to avoid calculating slew rate repeatedly. Experimental results show that our algorithm maximizes routing resources over obstacles and saves routing resources outside obstacles. Compared with the conventional OARSMT algorithm, our algorithm reduces the wire length outside obstacles by as much as 18.74% and total wire length by as much as 6.03%. Our algorithm improves the latest related algorithm by approximately 2% in terms of wire length within a reasonable running time. Additionally, calculating the slew rate only accounts for approximately 15% of the total runing time.