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441.
文中描述了一种自偏置型锁相环电路,通过采用环路自适应的方法得到一个固定的阻尼系数ξ以及带宽和输入频率的比值ωN/ωREF,从而保证环路的稳定。传统锁相环电路设计需要一个固定的电荷泵充放电电流和固定的VCO增益,这样才能保持系统的稳定性。但是当工艺发展到深亚微米尤其是65 nm以下的时候,芯片的供电电压都在1 V以下且器件的二级效应趋于严重,此时要得到一个固定的电流值或者固定的VCO增益是很困难的。自偏置锁相环解决了这个问题,由于采用了自适应环路的设计方法,使得系统受工艺、温度和电压的影响非常小,而且锁定范围更大。可以广泛应用于时钟发生器以及通信系统。芯片采用SMIC标准低漏电55 nm CMOS工艺制造,测试均方抖动为3.8 ps,峰-峰值抖动25 ps。 相似文献
442.
研究了一种用于微处理器时钟同步PLL的高带宽低噪声的压控振荡器(VCO),该VCO采用了交叉耦合的电流饥饿型环形振荡器,通过改善其控制电压变换电路,大大拓宽了压控增益的线性范围,消除了振荡器对控制电压的影响,降低了输出时钟的相位噪声.基于CSMC 3.3 V 0.35 μm CMOS工艺的仿真结果表明,取延迟单元沟道长度为1 μm、中心频率为365 MHz时,压控增益为300 MHz/V,其线性区覆盖范围是30~700 MHz,在偏离中心频率600 kHz处的相位噪声为-95 dB/Hz,低频1/f噪声在-20 dB/Hz以下.该VCO可以通过适当减小延迟单元沟道长度来拓宽压控增益线性范围. 相似文献
443.
This paper proposes a sigma-delta fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system.With reasonable frequency planning,the system can be used in multi-standard wireless communication applications(GSM,WCDMA,GPRS,TD-SCDMA,WLAN(802.11a/b/g)).The implementation is achieved by a 0.13μm RF CMOS process.The measured results demonstrate that three quadrature VCOs(QVCO) continuously cover the frequency from 3.1 to 6.1 GHz(65.2%),and through the successive divide-by-2 prescalers to achieve the frequency from 0.75 to 6.1 GHz continuously.The chip was fully integrated with the exception of an off-chip filter.The entire chip area is only 3.78 mm~2,and the system consumes a 21.7 mA@1.2 V supply without output buffers.The lock-in time of the PLL frequency synthesizer is less than 4μs over the entire frequency range with a direct frequency presetting technique and the auxiliary non-volatile memory(NVM)can store the digital configuration signal of the system,including presetting signals to avoid the calibration process case by case. 相似文献
444.
An integrated low-phase-noise voltage-controlled oscillator(VCO) has been designed and fabricated in SMIC 0.18μm RF CMOS technology.The circuit employs an optimally designed LC resonator and a differential cross-coupling amplifier acts as a negative resistor to compensate the energy loss of the resonator.To extend the frequency tuning range,a three-bit binary-weighted switched capacitor array is used in the circuit.The testing result indicates that the VCO achieves a tuning range of 60%from 1.92 to 3.35 GHz.The phase noise of the VCO is -117.8 dBc/Hz at 1 MHz offset from the carrier frequency of 2.4 GHz.It draws 5.6 mA current from a 1.8 V supply.The VCO integrated circuit occupies a die area of 600×900μm~2.It can be used in the IEEE802.11 b based wireless local network receiver. 相似文献
445.
相对于现在流行的FLASH型存储器,新型阻变存储器(resistive-RAM,RRAM)有很多优势,比如较高的存储密度和较快的读写速度。而针对RRAM的读写操作特性,提出了一种适用于新型阻变存储器的提供操作电压的电路。该方案解决了新型存储器需要外部提供高于电源电压的操作电压的问题,使得阻变存储器能应用于嵌入式设备。同时,对工艺波动和温度波动进行补偿,从而降低了阻变存储器的读写操作在较差的工艺和温度环境下的失败概率,具有很强的实际应用意义。该设计采用0.13μm标准CMOS 6层金属工艺在中芯国际(SMIC)流片实现,测试结果表明,采用此电路的RRAM能正确地进行数据编程和擦除等操作,测试结果达到设计要求。 相似文献
446.
447.
448.
A low-phase-noise LC-VCO with an enhanced-Q varactor for use in a high-sensitivity GNSS receiver 总被引:1,自引:1,他引:0
An LC-VCO with an enhanced quality factor(Q) varactor for use in a high-sensitivity GNSS receiver is presented.An enhanced A-MOS varactor is composed of two accumulation-mode MOS(A-MOS) varactors and two bias voltages,which show the improved Q and linearization capacitance-voltage(C-V) curve.The VCO gain(K_(vco)) is compensated by a digital switched varactors array(DSVA) over entire sub-bands.Based on the characteristics of an A-MOS,the varactor in a DSVA is a high Q fixed capacitor as it is switched off,and a moderate Q tuning varactor when it is switched on,which keeps the maximal Q for the LC-tank.The proposed circuit is fabricated in a 0.18μm 1P6M CMOS process.The measured phase noise is better than -122 dBc/Hz at a 1 MHz offset while the measured tuning range is 58.2%and the variation of K_(VCO) is close to±21%over the whole of the sub-bands and the effective range of the control voltage.The proposed VCO dissipates less than 5.4 mW over the whole operating range from a 1.8 V supply. 相似文献
449.
This paper proposes LC voltage‐controlled oscillator (VCO) phase‐locked loop (PLL) and ring‐VCO PLL topologies with low‐phase noise. Differential control loops are used for the PLL locking through a symmetrical transformer‐resonator or bilaterally controlled varactor pair. A differential compensation mechanism suppresses out‐band spurious tones. The prototypes of the proposed PLL are implemented in a CMOS 65‐nm or 45‐nm process. The measured results of the LC‐VCO PLL show operation frequencies of 3.5 GHz to 5.6 GHz, a phase noise of –118 dBc/Hz at a 1 MHz offset, and a spur rejection of 66 dBc, while dissipating 3.2 mA at a 1 V supply. The ring‐VCO PLL shows a phase noise of –95 dBc/Hz at a 1 MHz offset, operation frequencies of 1.2 GHz to 2.04 GHz, and a spur rejection of 59 dBc, while dissipating 5.4 mA at a 1.1 V supply. 相似文献
450.
AMBE-2000具有话音质量高、编码速率可变、配置灵活等特点,在卫星通信、安全通信、数字移动无线电领域得到了广泛应用。根据关键管脚功能以及时序要求使用4片ABME-2000设计实现了双路话音编解码器,每个AMBE-2000只完成编码或解码功能。为了保证话音质量,采用CD74HC4046A进行编解码时钟的同步设计。设计的双路话音编解码模块经试验验证,话音清晰,满足系统要求。 相似文献