一种10GHz 0.13µm CMOS 低杂散低抖动锁相环

介绍了一种10 GHz低杂散、低抖动锁相环电路。利用改进的压控振荡器和具有较小延迟复位时间动态鉴频鉴相器有效降低锁相环相位噪声,同时讨论了高频分频器噪声以及电荷泵电流失配的优化方法。电路采用中芯国际0.13µm 1.2V射频CMOS工艺实现。测量结果表明,锁相环RMS抖动为757 fs (1KHz到10MHz); 在10 kHz、1 MHz频偏处的相位噪声分别为-89与-118.1dBc/Hz;参考频率杂散低于-77dBc。芯片面积0.32 mm2,功耗30.6mW。     

一种用于10 Gb/s Serdes的40 nm CMOS锁相环

提出了一种应用于10 Gb/s高速串并接口电路(Serdes)的高性能锁相环。采用正交压控振荡器(QVCO)实现4路等相位间隔的5 GHz时钟,输出采用2分频单转差缓冲器,实现可忽略相差的8路等相位间隔的2.5 GHz时钟。电荷泵中采用负反馈技术,以提高电流匹配性能。在SMIC 40 nm工艺下完成设计,在 1.1 V的供电电压下,锁相环的总电流为7.6 mA,输出5 GHz时钟在10 kHz~100 MHz积分范围内的均方根抖动约为107 fs,芯片尺寸仅为780 μm×410 μm。     

变容二极管背靠背拓扑结构的性能分析

针对变容二极管在实际应用电路中,由于非线性所造成的寄生调制、频率抖动、频率失真、AM to PM噪声引入等问题,文中采用变容二极管背靠背拓扑结构(BBS),通过改善压控线性度来降低电路RF调制、频率抖动、相位噪声等影响,既能抑制非线性导致的寄生调制现象,又简化了调节电压。为目前广泛应用变容管作为电调元件的电路提供了参考。     

宽带高性能频率合成器设计

随着移动通信测试仪器的发展,宽带高性能频率合成器成为其设计的难点,文中利用双锁相环（PLL）结构和Σ-△小数分频技术,设计出一种高性能频率合成器。实现了2 000～4 000 MHz的频率覆盖和低于003 Hz的频率分辨率,全频段相噪均在-105 dBc/Hz@10 kHz以下。测试结果满足宽带高性能频率合成器的设计要求,具有较高的实用价值。     

L/S/C波段低相噪、单片锁相频率源实现

介绍一种在20 mm×20 mm PCB上实现L/S/C波段频率源的方法,当频率最高达4 820 MHz时,相位噪声达到-100 dBc/Hz@10 kHz。当步进设为2 MHz,环路带宽为100 kHz时,杂波抑制＞40 dBc,跳频时间＜200 μs;环路带宽为40 kHz时,杂波抑制＞60 dBc,跳频时间＜600 μs。可以应用于一些低端的接收机和校正源上,或是对杂散抑制要求不高的射频通信中。     

An investigation on the discrete-time nature of excess phase and jitter

Excess phase in oscillators or phase locked loops is a very important design specification typically modelled as a continuous time signal. In this article, we explain why, when the quantity of interest is jitter, excess phase should be treated as a discrete quantity. This treatment helps explaining noise folding in frequency dividers and analyse its consequences in phase locked loops.     

A coupled-inductor dual-mode switched voltage-controlled oscillator using GaN-on-Si HEMT technology

A coupled-inductors dual-mode switch cross-coupled pair voltage-controlled oscillator (VCO) was presented, adopting GaN-on-Si high-electron-mobility transistor technology. The coupled inductors create two resonant frequencies that cover a wide frequency range. The two continuous bands were achieved by using coupled inductors, and the fine-tuning is controlled by varactors. The low and high bands of the VCO were 2.77–3.11 GHz and 3–3.28 GHz, in the V_c range between 10 and 17 V, respectively, which corresponds to a 16.7% (510 MHz) tuning range. The lowest phase noise was ?123 dBc/Hz at an offset frequency of 1 MHz, and the highest output power was 17.7 dBm using a 7.5-V power supply.     

A CMOS oscillator for radiation-hardened,low-power space electronics

This article presents the design, manufacturing and test results of an on-chip CMOS oscillator, using a ring-oscillator, VCO based architecture. The oscillator generates a configurable square waveform clock signal to be used internally or externally to the IC that integrates it, with very low area (320 transistors, 112?×?148?µm) and power overhead (975?µW). The oscillator is integrated in a mixed signal IC which has been qualified for space applications, at a commercial 250?nm process. It enables the standalone operation of the IC without external oscillator and gives the possibility to clock other components and systems. In addition, it reduces the noise interference at PCB and chip level, optimising the performance of sensitive analogue parts. It was validated by radiation tests according to ESA standards’ procedures that the oscillator's functionality and characteristics do not deteriorate with TID levels up to 1Mrad. This approach can be easily adjusted to a wide range of frequencies, while significantly reducing the cost and power budget of space qualified systems with small design effort trade-off.     

A 5-GHz low-voltage and low-power CMOS LC voltage controlled oscillator for 802.11a wireless LAN applications

In this paper, a low phase noise and low power 5.15?GHz LC-tank VCO is presented and analysed. The phase noise achieved is??91,??116 and??126?dBc/Hz at 100?KHz, 1?MHz and 3?MHz offsets respectively from the carrier frequency of 5.15?GHz, with 1.8?V power supply voltage and giving a very low power consumption of about 2.5?mW by considering the proposed oscillator topology, which consumes less power than the classical oscillator using the traditional differential transconductor pair. A broad tuning range has been achieved by means of standard mode PMOS varactors. The tunability of the designed VCO covers 530?MHz, from 4.78?GHz up to 5.31?GHz. Predicted performance has been verified by analyses and simulations using ELDO-RF tool with 0.35?µm CMOS TSMC parameters.