MC145163P型锁相频率合成器的原理与应用

Motolora公司的MC145163P是CMOS大规模集成锁相频率合成器,内部含有参考分频器、两个相位比较器和4位BCD/N分频器,配合环路滤波和压控振荡器就可以得到一个完整、实用的锁相频率合成器.文中介绍了MC145163P的基本性能,并结合实际应用详细介绍了由MC145163P和TTL压控振荡器74LS628组成的锁相频率合成电路,给出实际测量数据.     

一种用于时钟产生的低功耗电荷泵锁相环设计

设计了一种用于时钟产生的电荷泵锁相环(CPPLL),其压控振荡器(VCO)采用了新颖的带电流补偿的电流减法器结构。采用Charted2.5V、0.25μmCMOS工艺,整个芯片的面积为300μm×400μm,VCO输出频率范围为55MHz～322MHz。整个电路功耗低,VCO输出频率为240MHz时,功耗为6mW。Hspice仿真结果表明,VCO输出时钟为96MHz时,峰峰值抖动为320ps。     

Noise transfer characteristics and design techniques of a frequency synthesizer

This paper presents an exact method for the loop parameters’ calculation. The noise transfer functions of PLL based synthesizers are derived in the z-domain analysis. Through the comparison of the s-domain model with the z-domain model, we show that the noise peak from inherent sampling behaviors always exists in the loop, and the loop filter with the wide loop bandwidth doesn’t suppress it. Such a noise peak causes instability to the system. A stability limit of the wide loop bandwidth frequency synthesizer is extracted by the behavioral simulation using the z-domain model, which depends on the phase margin and the ratio between the reference frequency and the loop bandwidth.     

95GHz低相噪锁相源技术研究

基于毫米波锁相源相位噪声理论,明确指出采用低相位噪声的微波频率源可以有效改善毫米波锁相源相噪指标。利用低相位噪声的微波倍频源,结合谐波混频方式,设计出95GHz低相位噪声锁相频率源。测试结果表明,其相位噪声可以低至-90.44dBc/Hz@10kHz,验证了该设计方案的可行性。     

集成锁相环芯片Si4133的原理及应用

Si4133是Silicon Labs公司生产的单片集成锁相环电路,可广泛用于射频和中频频率合成。介绍了Si4133频率合成器芯片的工作原理和功能结构,并给出了该芯片的典型应用电路和使用方法。测试结果显示,该频率源相位噪声低,杂散低,具有较强的实用性。     

基于System View仿真的数字频率合成器

介绍了频率合成的原理，常用几种频率合成技术及其优缺点。选择最常用的数字频率合成技术检验其合成频率的效果，在动态系统仿真软件SystemView环境下设计构建了一个数字频率合成器．并对其进行仿真分析，仿真结果表明，在滤波器带宽和VCO的载波最大变化范围内，可产生多个频率稳定的输出信号，达到设计要求。     

CMOS锁相环PLL的设计研究

在阅读大量锁相近十年发表的英文文献的基础上,对锁相环的设计及特性做了深入的分析,并对锁相环的主要部件相频检测器和压控振荡器的结构和特性做了比较和总结。     

振动对SYK801型SAW VCO 频谱性能的影响

对ＳＹＫ８０１型声表面波压控振荡器（ＳＡＷ ＶＣＯ）在振动条件下的输出频谱性能进行了初步的探索和研究。介绍了这类型振荡器的振动灵敏度系数的表达式,初步分析影响振动灵敏度系数的主要因素,提出改善振动性能的技术措施。测试结果表明所采取的技术措施对改善振荡器的振动性能是有效的。     

一种低功耗低噪声自偏置锁相环电路

在飞速发展的物联网、可穿戴设备、医疗电子等小型化领域,小尺寸、低功耗是集成电路设计的重要指标。本文提出了一种低功耗、面积小、低相位抖动的锁相环电路。利用自偏置技术补偿锁相环的环路增益等参数,同时简化压控振荡器和电荷泵的电路结构,取得了面积、功耗、噪声以及环路稳定性的良好统一。该锁相环电路作为独立IP模块实现在SMIC 40nm工艺上,供电电压为2.5V/1.1V,最高输出频率至2.5GHz以上,总功耗为4.2mW,面积仅为0.02 mm2 (180um*110um)。     

A 1-V 4-GHz wide tuning range voltage-controlled ring oscillator in 0.18 μm CMOS

A new differential delay cell with complementary current control to extend the control voltage range as well as the operation frequency is proposed for low voltage and wide tuning range voltage-controlled ring oscillator (VCRO). The complementary current control can get rid of the restriction that control voltage is unable to cover the full range of power supply voltage in a conventional VCRO. A three-stage VCRO chip working with 1 V power supply voltage is constructed using 0.18 μm 1P6M CMOS process for verifying the efficacy of the proposed differential delay cell. Measured results of the VCRO chip show that a wide range of operation frequency from 4.09 GHz to 479 MHz, a tuning range of 88%, is achieved for the full range of control voltage from 0 to 1 V. The power consumptions of the chip are 13 and 4 mW for oscillation outputs of 4.09 GHz and 479 MHz, respectively. The measured phase noise is −93.3 dBc/Hz at 1 MHz offset from 4.09 GHz center frequency. The core area of the chip is 106 μm×76.2 μm.