一种低功耗宽频率调谐范围的伪差分环形VCO

设计了一种低功耗、宽频率调谐范围的伪差分环形压控振荡器(VCO).电路设计分为振荡环路设计和电流源设计两部分.在振荡器的振荡环路部分,提出了一种新颖的降低功耗的方法,即通过动态地调节接入振荡环路的锁存器,减小驱动电流,降低功耗;在振荡器的控制电源部分,采用gain-boost结构,设计了一款理想的可控双电流源,实现了振荡器的宽频率调谐范围.基于SMIC 65 nm工艺,在1.8V工作电压下,对振荡器进行了后仿验证.结果表明,在频率为900 MHz时,振荡器的功耗仅为3.564 mW;当控制电压在0.6～1.8 V变化时,振荡器的频率调谐范围可宽达0.495 ～1.499 GHz.     

调频连续波SAR非线性误差的开环校正方法

针对FMCW (Frequency Modulated Continuous Wave) SAR(Synthetic Aperture Radar)调频非线性误差对一维聚焦性能影响和该误差校正问题,该文引入VCO(Voltage Controlled Oscillator)调频非线性高阶误差模型,从理论推导、定量分析了调频非线性误差对信号的具体影响.在VCO工作稳定、随时间电漂移度较小的前提下,提出了一种基于开环的FMCW SAR非线性校正方法.该方法首先一次补偿谐波误差,以信号压缩指标性能最优为收敛准则,通过迭代来校正因输入电压的更新和VCO电漂移及热噪声而引起抖动的高阶误差,进而对信号的调频非线性进行校正.信号仿真和实测数据处理结果表明该方法能对FMCW SAR信号源的调频非线性误差进行稳健、有效的校正,并且与传统的开环软件校正方法相比,该方法无需构建复杂的误差模型,具有简单、经济、运算量较小等优点.     

A wide band differentially switch-tuned CMOS monolithic quadrature VCO with a low Kvco and high linearity

A wide band, differentially switch-tuned CMOS monolithic LC-VCO is presented in this paper, as well as a frequency divider for high linearity, low Kvco quadrature signal generation. A linearity control logic is proposed. The Kvco linearity is improved to be lower than 17.68 MHz/V. By using the proposed CML DFF, the operating frequency of the frequency divider is increased by 20% with a power consumption of 3.6 mW. The proposed design has been fabricated and verified in a 0.18 μm CMOS process. The QVCO is tuned in a combined way of continuous technology and 4 bit binary switch capacitor array (SCA) discrete tuning technology. The measurement indicates that the QVCO has a 19.7% tuning range from 1.816 to 2.213 GHz. The measured phase noise is −112.25 dBc/Hz at 1 MHz offset from the 1.819 GHz carrier and draws a current of 4.0 mA around at a 1.8 V supply.     

变压器反馈的超低功耗低相位噪声CMOSLC-VCO设计

设计了一种全集成交叉耦合变压器反馈的LC压控振荡器(LC-VCO),该VCO在电源电压低于阈值电压的情况下实现了超低功率消耗和低相位噪声.该超低功耗的VCO采用SMIC 0.18μm数模混合RF 1P6M CMOS工艺进行了流片验证.测试结果表明:电路在0.4V电源供电和工作频率为2.433GHz时,相位噪声为-125.3dBc/Hz(频偏1MHz),核心直流功耗仅为720μW.芯片的工作频率为2.28～2.48GHz,调谐范围为200MHz(8.7%),电路的优值为-193.7dB,信号的输出功率约为1dBm.该VCO完全可以满足IEEE 802.11b接收机的应用要求.     

一种2.2～5.5G宽带低相位噪声LC VCO设计

论文基于BiCMOS工艺,采用了8个LC VCO并列的工作模式实现了2.2～5.5 GHz的带宽范围的LC VCO,每个LC VCO可以进行单独的调节.在LC VOC的核心电路中采用电阻代替电流镜方式以及在输出处增加了两个三极管限幅,以得到较低的相位噪声.在各个LC VCO的中心频率处其相位噪声优于-96 dBc@100 kHz.当电源电压为5 V时,各个LC VCO的工作电流为3.2 mA～4.2 mA.     

一种高速低过冲电荷泵电路的设计

为了有效降低传统电荷泵电路的充放电过冲电流,提高电荷泵输出控制电压的稳定性,提出、设计并实现了一种高速低过冲的电荷泵结构,该电路适用于高速锁相环及时钟数据恢复电路.电路在电源电压为1.2 V的0.13 μm CMOS工艺下设计实现,并对版图数据进行了HSPICE模拟,其结果表明,电路在2.5 GHz的速度下能很好的工作,同时电流过冲相比传统电荷泵下降了70%.     

一个4.2至5吉赫兹，低相位噪声，低调谐增益，等子频带间距的电感电容型压控振荡器

随着电感电容型压控振荡器调谐频率的增加,综合设计其中的负阻单元及可变电容,以同时达到宽调谐范围、低相位噪声、等子频带间距和低调谐增益输出频率的目标正变得越来越困难。本文中的压控振荡器通过设计一组开关可变电容阵列来解决这个问题,我们在0.18 μm CMOS工艺上实现了这个设计,并优化了相位噪声性能。测试表明,1兆赫兹频偏处的相位噪声达到-120dBc/Hz,调谐范围为4.2吉赫兹至5吉赫兹,调谐增益为8-10MHz/V,压控振荡器在1.5伏电源电压下至多消耗4毫安电流。     

A 6 GHz high power and low phase noise VCO using an InGaP/GaAs HBT

A 6 GHz voltage controlled oscillator (VCO) optimized for power and noise performance was designed and characterized. This VCO was designed with the negative-resistance (Neg-R) method, utilizing an InGaP/GaAs hetero-junction bipolar transistor in the negative-resistance block. A proper output matching network and a high Q stripe line resonator were used to enhance output power and depress phase noise. Measured central frequency of the VCO was 6.008 GHz. The tuning range was more than 200 MHz. At the central frequency, an output power of 9.8 dBm and phase noise of -122.33 dBc/Hz at 1 MHz offset were achieved, the calculated RF to DC efficiency was about 14%, and the figure of merit was -179.2 dBc/Hz.     

InGaP/GaAs HBT单管6GHz 大功率低噪声压控振荡器

A 6 GHz voltage controlled oscillator （VCO） optimized for power and noise performance was designed and characterized. This VCO was designed with the negative-resistance （Neg-R） method, utilizing an InGaP/GaAs hetero-junction bipolar transistor in the negative-resistance block. A proper output matching network and a high Q stripe line resonator were used to enhance output power and depress phase noise. Measured central frequency of the VCO was 6.008 GHz. The tuning range was more than 200 MHz. At the central frequency, an output power of 9.8 dBm and phase noise of-122.33 dBc/Hz at 1 MHz offset were achieved, the calculated RF to DC efficiency was about 14%, and the figure of merit was -179.2 dBc/Hz.     

宽带锁相环中的快速频带切换电路

首先讨论了普通频带切换电路及使用它的锁相环的电路结构,指出了其存在切换频带时间较长的问题,进而提出并分析了一种改进的频带切换电路。该电路在锁相环切换频带时,产生与输入参考时钟同步的复位信号用于复位鉴频鉴相器(PFD)和环路分频器,从而加快了锁相环频带的切换。该电路基于smicRF 0.18μm 1.8V CMOS工艺设计和流片验证,测试结果显示与普通频带切换电路相比,改进的频带切换电路明显的减少了频带切换时间。