EEAODR: An energy‐efficient ad hoc on‐demand routing protocol for mobile ad hoc networks

Mobile ad hoc networks (MANETs) are characterized by random, multi‐hop topologies that do not have a centralized coordinating entity or a fixed infrastructure that may change rapidly over time. In addition, mobile nodes operate with portable and finite power sources. In this work, we propose an energy‐efficient routing protocol for MANETs to minimize energy consumption and increase the network's consistency. Traditional works mainly focused on the shortest path‐based schemes to minimize energy, which might result into network failure because some nodes might exhaust fast as they are used repetitively, while some other nodes might not be used at all. This can lead to energy imbalance and to network life reduction. We propose an energy‐efficient ad hoc on‐demand routing protocol that balances energy load among nodes so that a minimum energy level is maintained among nodes and the network life increases. We focused on increasing the network longevity by distributing energy consumption in the network. We also compared the simulation results with a popular existing on‐demand routing protocol in this area, AODV, to establish the superiority of our approach. Copyright © 2009 John Wiley & Sons, Ltd.     

基于电源管理技术降低嵌入式系统功耗的研究

嵌入式处理器产品既要求提高其性能又要求降低功耗,这是互相矛盾的两个方面。但是,高性能处理必须增加计算复杂度并加快时钟速率,如果采用权宜之计的节省功耗设计方案,是很难实现的。介绍利用B lackfin数字信号处理器系列产品固有的动态电源管理方法来管理功耗,以便在具体的嵌入式应用中优化性能与功耗的关系,较好地解决降低嵌入式系统功耗问题。     

一个高性能低功耗10位30MS/s流水线A/D转换器

介绍了一个10位30M采样率流水线A/D转换器，通过采用运放共享技术和动态比较器，大大降低了电路的功耗. 在采样保持电路中使用一种新颖的自举（bootstrap）开关，减小了失真，使得电路在输入信号频率很高时仍具有很好的动态性能. 还提出了一种新的偏置电路结构，为增益提高运放提供了一个稳定且精确的偏置，使得增益提高运放具有较大的电压摆幅. 在30MHz采样时钟，29MHz输入信号下测试，可以得到9.16bit有效位的输出，在输入信号为70MHz时，仍然有8.75bit有效位. 电路积分非线性的最大值为0.     

基于La0.7Sr0.3FeO3的微结构乙醇气体传感器的研制

以La_0.7Sr_0.3FeO₃为敏感材料，设计制成了一种新型的共平面结构气体传感器.基于有限元分析软件Ansys对该传感器结构进行了优化设计.实验测得该传感器对于500ppm浓度乙醇气体的灵敏度为8.0，功耗为261mW，是同种敏感材料烧结型传感器功耗的2/3，响应时间约为1.5s，恢复时间约为2.5s，是一种功耗低、灵敏度高、稳定性好的微结构乙醇气体传感器.     

低压逻辑器件的发展

轻便个人电脑推动了低压逻辑芯片的研究开发。芯片电压降低后能显著减少功耗,不仅是轻便电脑所必须,对于工作站也不可少。大规模半导体存储器随着密度加大也必须降低工作电压,3.3V为低压标准已成为定局,未来还会出现新的、更低的低压标准。本文归纳和预测从1992年至2000年供电电压、沟道尺寸、集成元件数及微处理器速度等技术指标。     

An Integrated Framework for the Design and Optimization of SOC Test Solutions

We propose an integrated framework for the design of SOC test solutions, which includes a set of algorithms for early design space exploration as well as extensive optimization for the final solution. The framework deals with test scheduling, test access mechanism design, test sets selection, and test resource placement. Our approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests and power consumption. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. We have made an implementation of the proposed heuristic used for the early design space exploration and an implementation based on Simulated Annealing for the extensive optimization. Experiments on several benchmarks and industrial designs show the usefulness and efficiency of our approach.     

小面积低功耗掩膜ROMASIC设计

本文介绍了一种利用0.6μm单硅双铝双阱CMOS工艺实现的4Kbit掩膜ROM专用集成电路设计(ASIC).ROM单元应用串行结构,整个芯片的面积为0.082mm².在5伏电源下,功率延迟积为0.036PJ/bit,最大工作电流为1.2mA,最大静态漏电流为0.1μA.采用一种新颖的灵敏放大器有效地提高了ROM的访问速度,ROM的访问时间为36ns.     

柴油发电机组安装技术

阐述了柴油发电机组安装技术，解释了电发机组一些常见术语和定义，提供了康明斯电力系统柴油发电机组快速估算通风面积、燃油消耗和消噪计算公式。     

一个1GHz两倍泵的多端口寄存器堆的设计

对于流水线型的超大规模微处理器,通常采用多端口的寄存器堆暂存中间数据,这些读写操作势必增加寄存器堆的芯片面积和功耗。因此提出一种基于double-pumped的采样时钟,在一个系统时钟周期内用一根复用地址线顺序完成读写操作,从而大大减少芯片面积,并降低系统功耗。采用1.2V,0.13!m的CMOS工艺进行仿真,结果显示该2读1写寄存器堆在1GHz工作频率下,其数据读取时间仅为546ps。     

基于多层极小支配集聚类的WSN路由算法研究

提出了对随机聚类方法加以改进的新型多层极小支配集聚类算法，首先讨论了图论中的极小支配集算法，并根据实际需要提出了一种改进的简化近极小支配集的算法，大大降低了计算极小支配集的复杂程度，然后讨论了极小支配集应用在无线传感器网络聚类的实现，最后验证了该算法在能耗方面的性能改进。