乘积码在片上网络中的应用研究

研究了一种适用于片上网络(NoC)的能够纠3个错码的乘积码,该码的行编码采用扩展汉明码,列编码采用奇偶交验码实现.给出了乘积码的编解码方法,在此基础上对乘积码功耗和复杂度进行了仿真并与现有的码进行了分析比较.最后,给出了乘积码功能验证结果,结果表明所设计的乘积码功能正确,适合在NoC中应用.     

A novel CMOS charge-pump circuit with current mode control 110 mA at 2.7 V for telecommunication systems

This paper presents a novel organization of switch capacitor charge pump circuits based on voltage doubler structures. Each voltage doubler takes a DC input and outputs a doubled DC voltage. By cascading voltage doublers the output voltage increases up to 2 times. A two-phase voltage doubler and a multiphase voltage doubler structures are discussed and design considerations are presented. A simulator working in the Q-V realm was used for simplified circuit level simulation. In order to evaluate the power delivered by a charge pump, a resistive load is attached to the output of the charge pump and an equivalent capacitance is evaluated. To avoid the short circuit during switching, a clock pair generator is used to achieve multi-phase non-overlapping clock pairs. This paper also identifies optimum loading conditions for different configurations of the charge pumps. The proposed charge-pump circuit is designed and simulated by SPICE with TSMC 0.35-μm CMOS technology and operates with a 2.7 to 3.6 V supply voltage. It has an area of 0.4 mm2; it was designed with a frequency regulation of 1 MHz and internal current mode to reduce power consumption.     

一种低功耗64倍降采样多级数字抽取滤波器设计

经典多级结构的数字抽取滤波器占用系统大量的功耗与面积资源,文章设计的改进型64倍降采样数字抽取滤波器采用由级联积分梳状滤波器、补偿FIR滤波器和半带滤波器组成,在保持Σ-ΔADC转换精度的约束下,实现了最大程度降低系统功耗与面积的设计目标。在多级级联积分梳状(CIC)滤波器的设计中,充分运用置换原则以优化各级级数并采用非递归结构实现方式,同时将多相结构运用到补偿滤波器与半带滤波器中,获得电路功耗与面积的明显降低。将Σ-Δ调制器输出信号作为测试激励,通过Matlab系统仿真、FPGA验证与FFT信号分析,得到的输出数据信噪比达到15bit有效位数精度,且系统速度满足要求。     

TD-SCDMA集群通信系统中的呼叫接纳控制策略研究

基于第三代(3G)移动通信系统的时分同步码分多址(TD-SCDMA)集群通信系统,可以承载不同类型的集群业务,并能够为用户提供服务质量(QoS)保证。在无线网中提供QoS保证,呼叫接纳控制(CAC)扮演着重要的角色。在学习总结常规移动通信系统CAC方面研究成果的基础上,结合集群通信的特点,给出了适用于TD-SCDMA集群通信系统的呼叫接纳控制流程。     

直流供电系统的就近供电方案

对直流供电系统的就近供电方式和传统的供电方式进行比较,直流供电系统的就近供电方式在电源机房土建投资、电源设备能耗和机房环境建设等三个方面都具有节能降耗的优势。     

An Effective Power Reduction Methodology for Deterministic BIST Using Auxiliary LFSR

Power consumption for test vectors is a major problem in SOC testing using BIST. A new low power testing methodology to reduce the peak power and average power associated with scan-based designs in the deterministic BIST is proposed. This new method utilizes an auxiliary LFSR to reduce the amount of the switching activity in the deterministic BIST. Excessive transition detector (ETD) monitors the number of transitions in the test pattern generated by LFSR and the low transition pattern is generated for excessive transition region using an auxiliary LFSR. Experimental results for the larger ISCAS 89 benchmarks show that reduced peak power and average power can indeed be achieved with little hardware overhead compared to previous schemes.     

影响TD-SCDMA终端耗电的因素研究

本文结合TD-SCDMA系统及终端的技术特性,重点对网络侧影响终端耗电的因素进行了深入研究.通过外场试验的方式,对这些因素的实际影响进行了验证.一方面摸清了目前TD-SCDMA终端基本业务耗电状况,另一方面对影响终端耗电的因素进行了试验对比,对于推动TD-SCDMA终端产业的发展有着重大的技术意义和现实意义.     

Optical packet switching: A reality check

This paper presents an analysis of the energy consumption in a number of optical switch fabric architectures for optical packet-switched applications and compares them to electronic switch fabrics. Optical packet switching does not appear to offer any substantial power consumption advantages over electronic packet switching. Therefore, there is no compelling case for optical packet switching.     

基于耗尽型工艺的锂电池充电保护芯片设计

提出了一种基于耗尽型工艺的单节锂离子电池充电保护芯片设计。阐述了此芯片的设计思想及系统结构,并对芯片关键电路的独特设计方法及原理进行了详细分析,特别是基准电路和偏置电路,利用耗尽型工艺使电路具有非常低的电源启动电压和功耗。在Hspice中仿真了采用0.6μm的n阱互补金属氧化物半导体(CMOS)工艺制作全局芯片的测试结果。验证了此芯片具有过电压检测、过电流检测、0 V电池充电禁止等功能,可用于单节锂离子电池充电的一级保护。     

Power‐saving policies for annual energy cost savings in green computing

The concept of green computing is a step toward advanced information technology‐related data computations. There is an urgent need to develop sustainable mobile telecommunication networks subscribed by Telecommunication Regulatory Authority of India (TRAI). This paper aims at deploying major recommendations and directions in computing systems directed by regulating authorities. Green computing–based power‐saving policies include virtualization technique, power‐saving method, and recycling technique‐type solution components that we tried to embed in existing systems. The energy‐efficient green computing reserves the reliability and power of information‐driven technology. This research paper provides a comprehensive approach toward applying green mechanism by spotting the difference between energy consumption of current academic scenario and after embedding power‐saving policies of green computing. Moreover, an account has been maintained about the amount of energy preservation. The extraordinary energy‐ and cost‐saving features of green computing make environment sustainable and lively for future generations.