基于JTAG技术的Flash加载

主要介绍了目前世界上主要流行的一种Flash加载技术——利用JTAG技术加载Flash。文章分为3个部分。首先描述了JTAG加载Flash的原理。然后对JTAG加载Flash的优点做了说明。最后对实验性能做了详细分析。     

关于参数型copula函数的拟合检验

在金融和保险中,copula函数是一种构造多元相关分布函数的有力工具．然而,怎样选择一个适当的copula函数用于拟合数据,并没有找到统一的方法．因此,基于copula函数的经验分布,我们提出了一种用于检验具有某种特定参数结构的copula函数拟合数据优良性的方法,并得到了此检验的渐近性质．由于该检验统计量的极限分布依赖未知参数,我们采用非参数蒙特卡罗方法确定临界值．我们做了一个简单的模拟来验证本文提出的检验方法的功效．     

中兴通讯GGSN内容计费解决方案

主要介绍了中兴通讯GGSN内容计费解决方案的特点，最后介绍了内容计费的测试情况和设备应用情况。     

电子测量仪器的可靠性鉴定试验

本文主要描述如何进行电子测量仪器可靠性鉴定试验.     

COMBINATORIAL DESIGN APPROACHES FOR AUTOMATIC TEST GENERATION

The n-way combination testing is a specification-based testing criterion, which requires that for a system consisted of a few parameters, every combination of valid values of arbitrary n(n ≥ 2) parameters be covered by at least one test. This letter proposed two different test generation algorithms based on combinatorial design for the n-way coverage criterion. The automatic test generators are implemented and some valuable empirical results are obtained.     

Preliminary Design of ITER Test Blanket Module HC-SB Structure

The helium cooled solid breeder blanket that represents the main stream in relevant blanket concepts. It is considered as one of the main options for the fusion reactor. This concept have advantage as follows： （ 1 ） structure simpleness and stability, （ 2 ） no effect of MHD, （ 3 ） a good compatibility in different materials.     

A BIST-DFT technique for DC test of analog modules

Among test techniques for analog circuits, DC test is one of the simplest method for BIST application since easy to integrate test pattern generator and response analyzer are conceivable. Precisely, this paper presents such an investigation for a CMOS operational amplifier that is latter extended to active analog filters. Since the computation of fault coverage is still a controversy question for analog cells, we develop first an evaluation technique for optimizing the tolerance band of the measurements to test. Then, using some DFT solutions we derive single DC pattern and discuss the minimal number of points to test for the detection of defects. A response analyzer is integrated with a Built-in Voltage Sensor (BIVS) and provides directly a logic pass/fail test result. Finally, the extra circuitry introduced by this BIST technique for analog modules does not exceed 5% of the total silicon area of the circuit under test and detects most of the faults.     

提高倒装芯片组装速度的在线测试

倒装芯片是一种性能价格比良好的互连技术 ,要求采用富有创新的操作 ,以满足KGD的测试方法和操作工艺的需要。在基片上贴装好以前应立刻进行测试以确保能够起作用的管芯才能被装配入到倒装芯片或者说印刷电路板上面。在线测试设备是一种能够满足这些性能要求和价格要求的设备     

STG-BASED VERIFICATION AND TEST GENERATION

This paper presents the techniques of verification and Test Generation(TG) for sequential machines (Finite State Machines, FSMs) based on state traversing of State Transition Graph(STG). The problems of traversing, redundancy and transition fault model are identified. In order to achieve high fault coverage collapsing testing is proposed. Further, the heuristic knowledge for speeding up verification and TG are described.     

Test sets for integer programs

In this paper I discuss various properties of the simplicial complex of maximal lattice free bodies associated with a matrixA. If the matrix satisfies some mild conditions, and isgeneric, the edges of the complex form the minimal test set for the family of integer programs obtained by selecting a particular row ofA as the objective function, and using the remaining rows to impose constraints on the integer variables.