不同光刻胶作保护层对a-IGZO TFT性能的影响

采用脉冲直流溅射的方式沉积IGZO膜层作为底栅结构TFT的有源层,并在背沟道上涂覆不同类型的光刻胶作为保护层,探讨不同保护层对器件电学特性的影响。经考察发现:采用光刻胶作为保护层时,保护层制作后短期内可维持器件的电学特性基本不变;但涂胶后暴露在空气中一定时间后,器件的电学特性开始衰退,尤其是阈值电压变化较明显,器件工作模式由增强型变为耗尽型,并推断光刻胶中溶剂接触到背沟道中IGZO,其化学反应导致沟道中氧脱附,载流子浓度增加。实验还发现:使用SU-8负性光刻胶作为保护层的器件,其电学特性衰退较小,在空气中放置一段时间后表现最稳定。     

基于S3C2410并行RGB信号的TFT模组串行RGB应用

文章简述了ARM处理器S3C2410 TFT信号驱动的相关原理,着重讲述了在S3C2410平台上,使用并行24位RGBTFT信号进行串行8位RGBTFT接口模组驱动的实现。采用该设计的实物显示效果良好,具备较强实用性。     

用于设备控制的双核驱动智能彩屏

本智能彩屏终端系统采用双核控制的方式使用C语言进行软件编程,解决了目前工控领域如何快速、低成本地从单色STN/FSTN液晶屏升级到真彩色TFT液晶屏的问题。     

基于陷落电荷效应的非晶硅TFT的开态电流模型

对非晶硅薄膜晶体管,提出基于陷落电荷和自由电荷分析的新方法。考虑到带隙中指数分布的深能态和带尾态,给出了基于阈值电压的开启区电流模型。定义阈值电压为栅氧/半导体界面处陷落于深能级陷阱态的电荷与陷落于带尾态的电荷相等时所对应的栅压。电流模型中,引入一陷落电荷参数β,此参数建立了电子的带迁移率与有效迁移率之间的关系。最后,将电流模型同时与Pao-Sah模型和实验数据进行比较和验证,结果表现出很好的一致性。     

通过LCD洁净间气流改善提升良品率

在传统的洁净间气流管理管控的基础上,着重介绍了TFT LCD制造业用洁净室系统的特性,以及在TFT LCD制造行业普遍出现的重要异常气流问题,提供了针对性的有效气流改善实施方案,并确认了气流改善,产品良率改善的效果,提出了未来TFT LCD洁净间气流改善的主要发展方向。     

Self-assembled monolayer modification of silver source-drain electrodes for high-performance pentacene organic field-effect transistors

We demonstrated excellent performance improvement of bottom-contact pentacene-based organic thin film transistors (OTFTs) fabricated at room-temperature with silver electrodes modified by self-assembled monolayers (SAMs) of binary mixtures of n-alkanethiol (n-decanethiol, HDT) and the fluorinated analog (3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,10-heptadecafluoro-1-decanethiol, FDT). The OTFTs with modified silver (Ag) electrodes exhibit carrier mobility of 0.21 cm²/V s, which is faster than most of bottom-contact pentacene-based OTFTs fabricated at room-temperature with gold (Au) electrodes. The threshold voltage is reduced from −30 V of the devices with Au electrodes to −5.4 V of the devices with modified Ag electrodes. The hole injection barrier is also reduced with modified Ag as indicated by ultraviolet photoemission spectroscopy. The enhancement of the saturation current and the mobility of the devices are due to both the reduction of hole injection barriers and the continuous grain size of pentacene on top of electrodes and dielectrics.     

Modeling of spiking analog neural circuits using organic semiconductor thin film transistors with silicon oxide nitride semiconductor gates

This paper uses the results of the characterization of amorphous semiconductor thin film transistors (TFTs) with the quasi-permanent memory structure referred to as silicon oxide nitride semiconductor (SONOS) gates, to model spiking neural circuits. SONOS gates were fabricated and characterized. In addition, MOSFETs using organic copper phthalocyanine (CuPc) were fabricated with these SONOS gates to demonstrate proof of concept performance. Analog spiking circuits were then modeled using these low performance TFTs to demonstrate the general suitability of organic TFTs in neural circuits. The basic circuit utilizes a standard comparator with charge and discharge circuits. A simple Hebbian learning circuit was added to charge and discharge the SONOS device. The use of these elements allows for the design and fabrication of high-density 3-dimensional circuits that can achieve the interconnect density of biological neural systems.     

多晶硅薄膜晶体管性能研究

文章首先提出多晶硅薄膜晶体管几种减小漏电流的方法,接着对采用超薄沟道结构和普通沟道结构的多晶硅薄膜晶体管的电特性进行对比,发现采用超薄沟道结构具有优越性,最后分析了器件特性与材料性质之间的关系。     

TFT-LCD阵列穿透率提升的研究

提高薄膜晶体管液晶显示器阵列基板的光利用效率的主要方法是提高开口率和穿透率。文章制作了低温多晶硅阵列穿透区多层膜,考察膜层以及结构对穿透率的影响,研究阵列光线穿透率提升的方法。结果表明,层间介质层（ILD）完成后不同折射率膜层接口对穿透率影响较大,平坦层（PL）的厚度对穿透率没有明显影响,导电膜氧化铟锡（ITO）厚度增加,穿透率下降。通过在阵列穿透区减少膜层数量和改变膜层组分,减少折射率差异较大的界面,可增加穿透率7%左右。     

Back channel etch chemistry of advanced a-Si:H TFTs

We report on the effects of back channel etch depth and etchant chemistry on the electrical characteristics of inverted staggered advanced amorphous silicon thin-film transistors. We found that the optimum amorphous silicon film thickness in the channel is about 800-1100 Å. Three dry etch, HBr + Cl₂, C₂F₆, and CCl₂F₂ + O₂, and one wet etch, KOH, chemistries are used for the back channel etch processing. We established that dry etch can be used for the back channel etch of amorphous silicon transistor without degrading its electrical characteristics.