Partial scan design and test sequence generation based on reduced scan shift method

This paper presents a partial scan algorithm, calledPARES (PartialscanAlgorithm based onREduced Scan shift), for designing partial scan circuits. PARES is based on the reduced scan shift that has been previously proposed for generating short test sequences for full scan circuits. In the reduced scan shift method, one determines proch FFs must be controlled and observed for each test vector. According to the results of similar analysis, PARES selects these FFs that must be controlled or observed for a large number of test vectors, as scanned FFs. Short test sequences are generated by reducing scan shift operations using a static test compaction method. To minimize the loss of fault coverage, the order of test vectors is so determined that the unscanned FFs are in the state required by the next test vector. If there are any faults undetected yet by a test sequence derived from the test vectors, then PARES uses a sequential circuit test generator to detect the faults. Experimental results for ISCAS'89 benchmark circuits are given to demonstrate the effectiveness of PARES.     

用于多种组装技术的厚膜导体复合结构

厚膜导体Ｐｄ－Ａｇ／Ａｕ、Ｐｔ－Ｐｄ－Ａｕ／Ａｕ平面复合结构，Ｐｄ－Ａｇ／Ａｕ立体复合结构可使多种组装技术相互兼容。立体复合结构还可有效地降低导体线电阻，减少线损耗。而且，其超声键合性尤佳     

电路板故障诊断中神经网络信息融合技术的应用

将信息融合技术应用到导弹电子设备的电路板故障诊断之中．提出了一种基于红外热成像实验的温度故障隶属度函数构造形式以及改进的BP神经网络算法。进行了BP神经网络信息融合故障诊断的实验研究．从结果看信息融合能较好地解决电路板元件故障诊断的不确定性问题。     

Memory management optimization problems for integrated circuit simulators

In hardware design, it is necessary to simulate the anticipated behavior of the integrated circuit before it is actually cast in silicon. As simulation procedures are long due to the great number of tests to be performed, optimization of the simulation code is of prime importance. This paper describes two mathematical models for the minimization of the memory access times for a cycle-based simulator.An integrated circuit being viewed as a directed acyclic graph, the problem consists in building a graph order on the vertices, compatible with the relation order induced by the graph, in order to minimize a cost function that represents the memory access time. For both proposed cost functions, we show that the corresponding problems are NP-complete. However, we show that the special cases where the graphs are in-trees or out-trees can be solved in polynomial time.     

红外焦平面器件脉冲驱动电路的小型化设计

代表着红外器件发展的主流方向的红外焦平面器件，其正常工作时需要驱动脉冲信号多达十几路，为了使红外焦平面阵列处于最佳工作状态，就必须设计出相应的驱动电路。提出了一种红外焦平面器件驱动电路的设计方法。该电路具有体积小、功率低及灵活性好等特点，为驱动电路以及成像系统的小型化提供了良好的技术基础。     

交流源作用下介观RLC电路系统量子态随时间的演化

根据量子不变量理论，同时考虑介观电容器极板间电子波函数的耦合作用和电路的耗散,研究介观RLC电路系统在交流电流源作用下动力学的演化过程，并且得到描述系统量子态随时间的演化算符.进一步的分析结果表明，介观RLC电路系统的波函数将由任意的初态演化到一般的压缩态. 关键词： 介观RLC电路 交变电源 不变量理论 时间演化算符     

MOS功率驱动高速脉冲激光器的研究

运用经典电路理论,对MOS功率管的开关特性、驱动原理进行了分析,导出了应用MOS功率管实现高速大电流开关应遵从的原则和方法,并成功地实现了光脉冲上升时间小于5ns、下降时间小于10ns,驱动电流达10～50AP-P激光器电源的要求.     

基于单片机控制的实验线路故障诊断系统

介绍了基于单片机控制技术的强电实验线路故障自动诊断系统的结构及功能,阐述了系统硬件设计、软件设计的基本原理．     

基于改善空间关联性的混沌控制

基于混沌信号的统计特性，提出了一种通过改善混沌信号的空间关联性实现混沌控制的方法.以Hénon离散混沌系统和四阶Chua's电路超混沌连续系统为例进行了数值研究，验证了这种控制方法的有效性.结果表明， 通过改善混沌信号之间的空间关联性， 混沌系统能以较快的速度收敛到它的平衡点或多种周期轨道. 关键词： 混沌控制 空间关联性 Hénon系统 四阶Chua's电路     

从模式I2C总线接口电路设计及其VLSI实现

提出了一种从模式的I^2C总线接口电路，该接口电路实现了对可变参数ASIC芯片的配置。该电路的设计使得可配置的ASIC芯片中参数配置所需要的芯片管脚大大减少。该方案已通过行为仿真和综合后门级时序仿真，并且用无锡上华0.6μmCMOS工艺实现。