自制纳米金属掩模对AlGaInPLED光提取效率的改进

In conventional light-emitting diodes (LED’s), the external efficiency is limited by total internal reflection at the semiconductor-air interface. An LED with a textured top surface can increase the light-extraction efficiency. This paper reports a new method to fabricate AlGaInP-based nanorod light emitting diodes (LEDs) by using self-assemble metal layer nano-masks and inductively coupled plasma (ICP). Light power measurements indicates that the scattering of photons considerably enhance the probability of escaping from the nanorod LEDs. The light-intensity of the nanorod LED is increased by 34% for a thin GaP window layer, and by 17% for 8 μm GaP window layer. The light power of the nanorod LED is increased by 25% and 13%, respectively.     

4W、22dB小信号增益K波段砷化镓单片微波集成功率放大器

本文报道了一种基于AlGaAs/InGaAs/GaAs pHEMT工艺的4W K波段单片微波集成功率放大器。该功放采用0.15 μm功率pHEMT工艺,并在片内实现了输入、输出端口的50欧姆阻抗匹配。当直流偏置电压为5.6V、直流偏置电流为2.6A时,该功放在19~22 GHz工作频段内可以输出4W的饱和功率,并达到22dB的小信号增益、13dB的输入回波损耗、25%的功率附加效率。     

一种用于接收机的低功耗自动增益控制环路

This paper proposes a new structure to lower the power consumption of a variable gain amplifier (VGA) and keep the linearity of the VGA unchanged. The structure is used in a high rate amplitude-shift keying (ASK) based IF-stage. It includes an automatic gain control (AGC) loop and ASK demodulator. The AGC mainly consists of six-stage VGAs. The IF-stage is realized in 0.18 μ m CMOS technology. The measurement results show that the power consumption of the whole system is very low. The system consumes 730 μ A while operating at 1.8 V. The minimum ASK signal the system could detect is 0.7 mV (peak to peak amplitude).     

A low power 12-b 40-MS/s pipeline ADC

This paper describes a 12-bit, 40-MS/s pipelined A/D converter (ADC) which is implemented in 0.18-μm CMOS process drawing 76-mW power from 3.3-V supply. Multi-bit architectures as well as telescopic operational transconductance amplifiers (OTAs) are adopted in all pipeline stages for good power efficiency. In the first two stages,particularly, 3-bit/stage architectures are used to improve the ADC's linearity performance. The ADC is calibration-free and achieves a DNL of less than 0.51 LSB and an INL of less than 1 LSB. The SNDR performance is above 67 dB below Nyquist. The 80-dB SFDR performance is maintained within 1 dB for input frequencies up to 49 MHz at full sampling rate.     

A 1.1 mW 87 dB dynamic range ΔΣ modulator for audio applications

This paper presents a 1.1 mW 87 dB dynamic range third order AS modulator implemented in 0.18 μm CMOS technology for audio applications.By adopting a feed-forward multi-bit topology,the signal swing at the output of the first integrator can be suppressed.A simple current mirror single stage OTA with 34 dB DC gain working under 1 V power supply is used in the first integrator.The prototype modulator achieves 87 dB DR and 83.8 dB peak SNDR across the bandwidth from 100 Hz to 24 kHz with 3 kHz input signal.     

Low-temperature deposition of transparent conducting Mn-W co-doped ZnO thin films

Mn-W co-doped ZnO(ZMWO) thin films with low resistivity and high transparency were successfully prepared on glass substrate by direct current(DC) magnetron sputtering at low temperature.The sputtering power was varied from 65 to 150 W.The crystallinity and resistivity of ZMWO films greatly depend on sputtering power while the optical transmittance and optical band gap are not sensitive to sputtering power.All the deposited films are polycrystalline with a hexagonal structure and have a preferred orientat...     

Above 700 V superjunction MOSFETs fabricated by deep trench etching and epitaxial growth

Silicon superjunction power MOSFETs were fabricated with deep trench etching and epitaxial growth,based on the process platform of the Shanghai Hua Hong NEC Electronics Company Limited.The breakdown voltages of the fabricated superjunction MOSFETs are above 700 V and agree with the simulation.The dynamic characteristics,especially reverse diode characteristics,are equivalent or even superior to foreign counterparts.     

A 12 bit 100 MS/s pipelined analog to digital converter without calibration

A 1.8 V 12 bit 100 MS/s pipelined analog to digital converter(ADC) in a 0.18μm complementary metal-oxide semiconductor process is presented.The first stage adopts a 3.5 bit structure to relax the capacitor matching requirements.A bootstrapped switch and a scaling down technique are used to improve the ADC's linearity and save power dissipation,respectively.With a 15.5 MHz input signal,the ADC achieves 79.8 dB spurious-free dynamic range and 10.5 bit effective number of bits at 100 MS/s.The power consumpt...     

Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic

Double gate FinFETs are shown to be better candidates for subthreshold logic design than equivalent bulk devices. However it is not so clear which configuration of DG FinFETs will be more optimal for subthreshold logic. In this paper, we compare the different device and circuit level performance metrics of DG FinFETs with symmetric, asymmetric, tied and independent gate options for subthreshold logic. We observe that energy delay product (EDP) shows a better subthreshold performance metric than power delay product (PDP) and it is observed that the tied gate symmetric option has ≈78% lower EDP value than that of independent gate option for subthreshold logic. The asymmetry in back gate oxide thickness adds to further reduction in EDP for tied gate and has no significant effect on independent gate option. The robustness (measured in terms of % variation in device/circuit performance metrics for a ±10% variation in design parameters) of DG FinFETs with various options has also been investigated in presence of different design parameter variations such as silicon body thickness, channel length, threshold voltage, supply voltage and temperature, etc. Independent gate option has been seen to be more robust (≈40% less) than that of tied gate option for subthreshold logic. Comparison of logic families for subthreshold regime with DG FinFET options shows that for tied gate option, sub-CMOS, sub-Domino and sub-DCVSL have almost similar and better energy consumption and robustness characteristics with respect to PVT variations than other families.