Automatic design rule adaptation of leaf cell layouts

The automatic adaptation of mask layouts to new design rules is considered. A new concept is presented that is based on geometric operations and mask compaction. The geometric operation MELT is discussed in detail; the other operations OR, AND, ANDNOT, OVERSIZE and UNDERSIZE are derived from it. The mask compaction consists mainly of a design rule analysis phase and the execution of a longest path algorithm. Contrary to symbolic compaction the mask compaction is based on polygon edges rather than symbols. With the example of the buried contact it is shown that even relatively complex design rule requirements may be met. Tests with several mask layouts sometimes led to overconstrained conditions. These conditions are located with the aid of a longest path algorithm that has not been applied to compaction programs up to now. Furthermore the inconsistent constraint cycles are broken by a fast jog generation algorithm.     

高斯电子束曝光系统

电子束光刻技术是纳米级加工技术的主要手段,在纳米器件加工、掩模制造、新器件新结构加工中扮演举足轻重的角色。虽然现在最先进的电子束聚焦技术可以得到几个纳米的电子束斑,但是由于邻近效应问题,依然很难使用电子束光刻技术得到接近其理论极限的纳米尺度图形,对电子束曝光系统的基本原理及其邻近效应校正技术进行了研究,并得到一些比较理想的曝光结果。     

Solder with discontinuous melting point in semiconductor laser arrays and stacks

High power semiconductor laser arrays must be mounted in the epitaxy-side down configuration for good heat transfer and so require a well-controlled solder. Selection of solder is very important in semiconductor laser arrays and stacks. Usually, the solder consists of two layers. The outer layer prevents In from oxidation. A new type of solder with several layers of Au between the two layers of In was made, which constitutes of multi-layer of W/Ni/Au/In/Cu. In packaging, the Au layer in the solder does not melt. Quick temperature decrease can avoid expansion of the solder. The solder cannot oxidize during packaging.     

某电子网版厂废水处理的设计与运行

根据某电子网版厂废水的特性,结合调试运行的经验教训,阐述了工艺设计方案的特点及先进的自控手段,并针对设计中存在的问题,提出了改进措施。     

Single mask dual damascene processes

Single mask dual damascene processes are described. The unique mask merges via and modified trench patterns. We design the mask’s trench area to have partial transmission using thin chromium or add phase shifted gratings in the trench area to achieve destructive interference for lowering the intensity. Optical proximity correction is used to obtain the desired lithography process window. Upon exposure, the trench results in a partial exposure while the via is fully exposed and a dual damascene (DD) photoresist profile is created within specifications. Following with an integrated etch can complete the DD image transfer into the underneath dielectric. A single mask DD process eliminates via/trench misalignment issues, can save up to one half of metal mask cost, and 50% of other processing costs. It is expected to also boost yield and improve product reliability.     

对国内印制电路板标准发展现状的思考

文章列举了四个案例,阐述了现行国内印制电路板标准与国外标准之间的差异,以此说明国内电子电路行业标准发展任重而道远。     

VLSI mask optimization: From shallow to deep learning

VLSI mask optimization is one of the most critical stages in manufacturability aware design, which is costly due to the complicated mask optimization and lithography simulation. Recent researches have shown prominent advantages of machine learning techniques dealing with complicated and big data problems, which bring potential of dedicated machine learning solution for DFM problems and facilitate the VLSI design cycle. However, uncertainty nature of state-of-the-art machine learning models have posed great challenges when developing alternative solutions. In this paper, we focus on a heterogeneous OPC framework that assists mask layout optimization. Instead of fitting neural networks for mask optimization tasks directly, a multi-class classification model is developed to capture design characteristics and hence determine the most suitable OPC engines. Experimental results have shown the efficiency and effectiveness of proposed frameworks that have the potential to be alternatives to existing EDA solutions.     

CMOS影像感应器构装——湿式无电镀镍沉积技术之最佳化

无电镀镍金（Electroless Nickel ＆ Immersion Gold;简称ENIG）沉积可以选择性地沉积于铝垫,由于此技术不必使用高成本之光阻微影制程,也不需真空溅镀制程,它可以降低制造成本。然而在实际制造大量生产时,常常面临到化学镀液很难控制之问题。经由精密控制其化学镀液中之一些重要参数,例如温度、pH值、还原剂、镍及稳定剂浓度等,可以明显提高制程性能,以满足量产需求。     

再流焊技术的新发展

主要针对SMT技术发生的巨大变化,对再流焊技术未来发展进行了简单的阐述。     

The effect of temperature and strain rate on the tensile properties of a Sn99.3Cu0.7(Ni) lead-free solder alloy

In this paper, the effect of temperature and strain rate of the lead-free solder alloy Sn_99.3Cu_0.7(Ni) was investigated. Tensile properties of this lead-free solder Sn_99.3Cu_0.7(Ni) at various temperatures and strain rates were determined and compared with those of the typical Pb-containing solder Sn₆₃Pb₃₇. During tensile tests of different temperatures and strain rates, the ultimate tensile strength (UTS) and 0.2% yield stress of the lead-free solder alloy Sn_99.3Cu_0.7(Ni) decreased with increasing test temperatures and decreasing strain rate. It was noted that mechanical properties of Sn99.3Cu0.3(Ni) showed strong temperature dependence and strain rate sensitivity in the tensile tests of various temperatures and strain rates. Temperature and strain rate impacted rigorously flowing behaviors of the lead-free solder Sn_99.3Cu_0.7(Ni) in the course of tensile deformation. The microstructure and fracture morphology of the lead-free solder Sn_99.3Cu_0.7(Ni) were analyzed by scanning electron microscope (SEM). In the SEM micro-graph of the fracture surface of this lead-free solder specimen tested, it was noted that increasing temperature affected the microstructure and morphology of fracture surface.