高速并行调制解调器中差错控制方法

本文简单介绍了适合高速并行调制解调器中差错控制的Reed-Solomon编码，提出了适合DSP软件实现的一整套的RS码的编码、译码实用方法，并对该编、译码法采用数字信号处理器TMS320C5410b进行仿真，对其性能与传统方法进行了对比。     

基于DSP的图像灰度校正

本文介绍了一个在用户视频环境下，采用典型非线性因子2.2进行非线性校正的公式；进而给出采用TMS320C2000进行图像灰度校正的软件设计方法。     

A new microtensile tester for the study of MEMS materials with the aid of atomic force microscopy

An apparatus has been designed and implemented to measure the elastic tensile properties (Young's modulus and tensile strength) of surface micromachined polysilicon specimens. The tensile specimens are “dog-bone” shaped ending in a large “paddle” for convenient electrostatic or, in the improved apparatus, ultraviolet (UV) light curable adhesive gripping deposited with electrostatically controlled manipulation. The typical test section of the specimens is 400 μm long with 2 μm×50 μm cross section. The new device supports a nanomechanics method developed in our laboratory to acquire surface topologies of deforming specimens by means of Atomic Force Microscopy (AFM) to determine (fields of) strains via Digital Image Correlation (DIC). With this tool, high strength or non-linearly behaving materials can be tested under different environmental conditions by measuring the strains directly on the surface of the film with nanometer resolution.     

Tests of ordered hypotheses in linkage in heredity

The asymptotic null distribution of the likelihood ratio test for two cases of ordered hypotheses in a particular genetic model is considered. A simple iterative process is proposed in order to get the restricted estimates. It is shown that both tests have asymptotically a chi-bar squared distribution and the same size. A simulation study is also conducted in order to compare the usual unrestricted test with the corresponding one of ordered hypotheses. Finally, the results are extended to some special cases.     

Techniques for estimating test length under random test

When a circuit is tested using random or pseudorandom patterns, it is essential to determine the amount of time (test length) required to test it adequately. We present a methodology for predicting different statistics of random pattern test length. While earlier methods allowed estimation only of upper bounds of test length and only for exhaustive fault coverage, the technique presented here is capable of providing estimates of all statistics of interest (including expected value and variance) for all coverage specifications.Our methodology is based on sampling models developed for fault coverage estimation [1]. Test length is viewed as awaiting time on fault coverage. Based on this relation we derive the distribution of test length as a function of fault coverage. Methods of approximating expected value and variance of test length are presented. Accuracy of these approximations can be controlled by the user. A practical technique for predicting expected test length is developed. This technique is based on clustering faults into equal detectability subsets. A simple and effective algorithm for fault clustering is also presented. The sampling model is applied to each cluster independently and the results are then aggregated to yield test lengths for the whole circuit. Results of experiments with several circuits (both ISCAS '85 benchmarks and other practical circuits) are also provided.This work was done while the author was with the Department of Electrical Engineering, Southern Illinois University, Carbondale, IL 62901.     

Energy minimization and design for testability

The problem of fault detection in general combinational circuits is NP-complete. The only previous result on identifying easily testable circuits is due to Fujiwara who gave a polynomial time algorithm for detecting any single stuck fault inK-bounded circuits. Such circuits may only contain logic blocks with no more thanK input lines and the blocks are so connected that there is no reconvergent fanout among them. We introduce a new class of combinational circuits called the (k, K)-circuits and present a polynomial time algorithm to detect any single or multiple stuck fault in such circuits. We represent the circuit as an undirected graphG with a vertex for each gate and an edge between a pair of vertices whenever the corresponding gates have a connection. For a (k, K)-circuit,G is a subgraph of ak-tree, which, by definition, cannot have a clique of size greater thank+1. Basically, this is a restriction on gate interconnections rather than on the function of gates comprising the circuit. The (k, K)-circuits are a generalization of Fujiwara'sK-bounded circuits. Using the bidirectional neural network model of the circuit and the energy function minimization formulation of the fault detection problem, we present a test generation algorithm for single and multiple faults in (k, K)-circuits. This polynomial time aggorithm minimizes the energy function by recursively eliminating the variables.     

Reducing Average and Peak Test Power Through Scan Chain Modification

Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result in frequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. The transitions embedded in both test stimuli and the responses are handled through scan chain modifications consisting of logic gate insertion between scan cells as well as inversion of capture paths. No performance degradation ensues as these modifications have no impact on functional execution. To reduce average and peak power, we herein propose computationally efficient schemes that identify the location and the type of logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.     

大连电视台分量电视车视频系统设计特点

本文介绍亚州第一台模拟分量电视车视频系统的设计思想,比较详细地阐述了该车的各种功能,总结了不同于复合电视车的新特点。     

一种数字语音通信系统的DSP实现

介绍了一种甚低频低码率数字通信系统的实现方案，该方案中的软件采用混合编程的方法，硬件则用DSP实现，文章给出了整个系统的DSP软硬件调试方法，并通过调试结果表明该方案具有很好的可行性和实时性。     

利用计算机辅助装调检测矩形大口径离轴非球面的方法研究

通过非球面的零位补偿法,完成了对矩形大口径离轴非球面镜的检测。先用光学设计软件Zemax从理论上分析了在检测中会出现的现象,并结合计算机辅助装调技术,确定在检测过程中相对敏感的自由度,然后控制这些量,使补偿器和非球面的相对关系与理论设计相吻合,在Zygo相位干涉仪上测得最终结果。在λ=632.8nm时,中心圆口径与两个边缘圆口径面形误差RMS分别为0.022λ,0.037λ,0.032λ。检测结果,达到预期目的。