通用数据访问模式的研究

运用面向对象的设计原则，将代理模式与工厂方法模式相结合，提出了一种新的通用数据访问模式。该模式可支持多种关系型数据库管理系统和数据驱动程序，通过将应用层与数据层隔离，大大减少了系统的耦合性，具有广泛的实际应用前量。     

词法分析及其C语言实现

介绍了编译过程的第一阶段——词法分析的功能和输出,词法分析器的实现模式及词法出错的处理,并在此基础上依据C语言的范式给出了设计C语言程序的词法分析器的基本思路和需要考虑的问题。     

去耦电容在PCB中的应用

介绍在PCB板上添加去藕电容进行EMC和信号质量的优化设计方法。详细说明在添加去耦电容时，去耦电容取值大小的计算、电容类型的选择、去耦电容的摆放、不同线路的频率和上升速度大小、线路板各层之间以及时钟的自协调频率的配合、防止共振的产生等这些应用去耦电容时关注和考虑的内容。     

基于HyperLynx的高速PECL交流耦合时钟设计

随着高速数据传输发展的需求,在高速IC之间的时钟路径变得越来越关键,成为影响系统性能、功耗及噪声的关键因素。PECL(正电压射极耦合逻辑)信号作为一种适合高速逻辑互联的电平标准,越来越多地应用在高速A/D转换器的时钟设计中。介绍了一种交流耦合形式的PECL高速时钟设计方法。在时钟的端接设计中,采用串联终端匹配和并联终端匹配改善信号完整性,并利用HyperLynx软件进行仿真,取得了良好的效果,对于实际电路设计有良好的指导作用。     

Mitigating the gateway bottleneck via transparent cooperative caching in wireless mesh networks

Wireless mesh networks (WMNs) have been proposed to provide cheap, easily deployable and robust Internet access. The dominant Internet-access traffic from clients causes a congestion bottleneck around the gateway, which can significantly limit the throughput of the WMN clients in accessing the Internet. In this paper, we present MeshCache, a transparent caching system for WMNs that exploits the locality in client Internet-access traffic to mitigate the bottleneck effect at the gateway, thereby improving client-perceived performance. MeshCache leverages the fact that a WMN typically spans a small geographic area and hence mesh routers are easily over-provisioned with CPU, memory, and disk storage, and extends the individual wireless mesh routers in a WMN with built-in content caching functionality. It then performs cooperative caching among the wireless mesh routers.We explore two architecture designs for MeshCache: (1) caching at every client access mesh router upon file download, and (2) caching at each mesh router along the route the Internet-access traffic travels, which requires breaking a single end-to-end transport connection into multiple single-hop transport connections along the route. We also leverage the abundant research results from cooperative web caching in the Internet in designing cache selection protocols for efficiently locating caches containing data objects for these two architectures. We further compare these two MeshCache designs with caching at the gateway router only.Through extensive simulations and evaluations using a prototype implementation on a testbed, we find that MeshCache can significantly improve the performance of client nodes in WMNs. In particular, our experiments with a Squid-based MeshCache implementation deployed on the MAP mesh network testbed with 15 routers show that compared to caching at the gateway only, the MeshCache architecture with hop-by-hop caching reduces the load at the gateway by 38%, improves the average client throughput by 170%, and increases the number of transfers that achieve a throughput greater than 1 Mbps by a factor of 3.     

The Effectiveness of Test in Controlling Quality Costs: A Conformability Analysis Based Approach

Test and inspection are an increasingly costly element of electronic system design and manufacture and so it is critical that the cost effectiveness of test and inspection are well understood. This paper presents techniques which may be used to assess test capability and hence the implied test quality costs of PCB level electronic circuits. The techniques presented are based on the electronic Conformability Analysis (eCA) approach which combines process capability indices and Failure Modes and Effects Analysis with a cost mapping procedure. It introduces a new measure of test capability based on the widely used process capability measure C _pk. This analysis allows the quality costs associated with design and manufacture induced faults to be estimated and the effectiveness of test strategies in reducing these costs to be determined. It allows the trade-off between quality costs and the component, manufacturing process and test costs to be explored. The technique has been applied to analogue & mixed signal, safety critical circuits from automotive systems.     

Modular analysis and design of log-domain circuits based on LIN↔ELIN transformations

We systematized and developed some procedures for the modular design of externally-linear internally nonlinear (ELIN) circuits resulting in a general LIN↔ELIN transformation procedure. This one was also extended to analysis of these types of circuits. The procedure is exemplified on log-domain circuits. In the design one starts with the linear block diagram (LIN) described by transfer functions and one substitutes directly each linear building block by a corresponding nonlinear one. The parameters of each nonlinear component depend on the given parameters of its linear correspondent. Input F ⁻¹ and output F blocks are added. In the analysis one identifies the nonlinear basic circuit components and each of them is substituted by its corresponding linear building block. Input and output F ⁻¹-F cells are removed. The ideal transfer function can be calculated on the linear block diagram now. The LIN↔ELIN transformations make a direct connection between equivalent linear and ELIN circuits, simplify their design and analysis procedures and permit the development of CAD procedures.     

Design of smallest size two-dimensional linear-phase FIR filters with magnitude error constraint

This paper presents an online procedure that produces the smallest feasible size of two-dimensional FIR filters with prescribed magnitude error constraint. The procedure uses the mean square normalized error of constrained and unconstrained least-square filters to produce the initial and the subsequent sizes that converge to the smallest feasible one in a few iterations, where the constrained least-square filters are defined as the least-square filters satisfying the magnitude error constraint. The procedure finally returns a smallest size filter that satisfies the magnitude error constraint and has least total squared magnitude error. Design examples of diamond-shaped, rectangular, and elliptic filters are provided, and comparisons with an exhaustive search are given.     

A versatile signal flow graph realization of a general transfer function by using CDBA

A general synthesis procedure is given for a versatile signal flow graph realization of a general transfer function by using current differencing buffered amplifier (CDBA). The proposed configuration uses n+1 CDBAs, n capacitors and at most 2n+4 resistors. This number of resistors can be reduced to n+1 for special cases. The circuit is eligible to obtain a variety of transfer characteristics with the same common denominator polynomial, and it is easily converted to different modes of operations. It is straightforward to find the values of the passive elements from the coefficients of the transfer function to be realized. Simulations results are obtained by using commercially available active component AD844 and CMOS technology as well. All of these make the proposed circuit attractive.     

计算机动画在教学片中的设计和应用

计算机动画是多媒体应用系统中不可缺少的重要技术之一，动画作为人们喜闻乐见的信息表现形式，在计算机的多种信息媒体中受到了人们的普遍欢迎，其应用范围从专业影视片的制作、广告宣传、工程设计到教育、教学培训几乎无处不有。主要介绍计算机动画在教学片中的设计和应用。