Gate-edge charges related effects and performance degradation in advanced multiple-gate MOSFETs

This paper analyzes the influence of negative charges (NC) located at the gate edges on the advanced MOSFETs behavior, paying particular attention to the subthreshold slope, S, maximum transconductance, G_mmax, and analog figures of merit, such as transconductance over drain current ratio, G_m/I_D, output conductance, G_D, Early voltage, V_EA, and intrinsic gain. General trends obtained by two-dimensional numerical simulations on double-gate (DG) structures are whenever possible qualitatively correlated with experimental data obtained on FinFETs. We show that the presence of negative charges at the gate edges while degrading the subthreshold behavior and analog figures of merit (especially for long-channel devices) can result in apparent improved control of short-channel effects and higher G_mmax. The origin of such twofold impact of negative charges at the gate edges on the device behavior is also analyzed by 2-D device simulations and a simplified two-transistors model.     

LKE and BGI Lorentzian noise in strained and non-strained tri-gate SOI FinFETs with HfSiON/SiO2 gate dielectric

The LKE (Linear Kink Effect) and BGI (Back-Gate-Induced) Lorentzians present in the drain current noise spectra of fully-depleted tri-gate n- and pFinFETs, fabricated on sSOI and SOI substrates with HfSiON/SiO₂ gate dielectric are described.It is shown that the analysis of the parameters of LKE and BGI Lorentzians allows to find the values of (С_eq/m′β²), β and [j_EVB/(m′β)²] where С_eq is the body-source capacitance, m′ ≈ 1, β is the body factor and j_EVB is the density of the EVB current flowing through the gate dielectric.As a result, the following effects were observed for the first time: (i) (С_eq/m′β²) decreases with increasing gate overdrive voltage |V^∗| and depends sub-linearly on the effective fin width W_eff under strong inversion conditions; (ii) in depletion and weak inversion where (С_eq/β²) is independent of |V^∗| the proportionality (С_eq/β²) ∝ W_eff is observed for an effective width W_eff ? 0.87 μm while (С_eq/β²) becomes independent on W_eff for W_eff < 0.87 μm; (iii) the value of β for the FinFETs investigated is higher than for their planar counterparts; (iv) in spite of the fact that strain affects the barrier height at the Si/SiO₂ interface, the EVB current densities j_EVB for sSOI and SOI devices are equal; (v) the values of j_EVB for the HfSiON/SiO₂-devices are much higher than for the HfО₂/SiO₂-ones studied previously. It is also shown that the gate overdrive voltage |V^∗| at which the LKE Lorentzians start to appear is as low as 0.25 V.     

An analytical compact model for Schottky-barrier double gate MOSFETs

An analytical and explicit compact model for undoped symmetrical silicon double gate MOSFETs (DGMOSFETs) with Schottky barrier (SB) source and drain is presented. The SB MOSFET can be studied as a traditional MOSFET where the doped source/drain regions have been replaced by a metal contact. Due to particular features of this new structure, the main transport mechanisms of these devices differ from those found in traditional MOSFETs. The model developed in this paper is based on a previously published DGMOSFET model which has been extended to include the characteristic tunneling transport mechanisms of SB MOSFET.The proposed model reproduces the well known ambipolar behavior found in SB MOSFET for a wide range of metal source and drain contacts specified through different values of their work function. The model has been validated with numerical data obtained by means of the 2D ATLAS simulator, where a SB DGMOSFET structure has been defined and characterized in order to obtain the transfer and output characteristics for several bias configurations. Devices with two channel lengths (2 μm and 3 μm) has been simulated and modeled.     

Impact of SOI thickness on device performance and gate oxide reliability of Ni fully silicide metal-gate strained SOI MOSFET

This study investigates the effects of oxide traps induced by SOI of various thicknesses (T_SOI = 50, 70 and 90 nm) on the device performance and gate oxide TDDB reliability of Ni fully silicide metal-gate strained SOI MOSFETs capped with different stressed SiN contact-etch-stop-layer (CESL). The effects of different stress CESLs on the gate leakage currents of the SOI MOSFET devices are also investigated. For devices with high stress (either tensile or compressive) CESL, thinner T_SOI devices have a smaller net remaining stress in gate oxide film than thicker T_SOI devices, and thus possess a smaller bulk oxide trap (N_BOT) and reveal a superior gate oxide reliability. On the other hand, the thicker T_SOI devices show a superior driving capability, but it reveals an inferior gate oxide reliability as well as a larger gate leakage current. From low frequency noise (LFN) analysis, we found that thicker T_SOI device has a higher bulk oxide trap (N_BOT) density, which is induced by larger strain in the gate oxide film and is mainly responsible for the inferior gate oxide reliability. Presumably, the gate oxide film is bended up and down for the p- and nMOSFETs, respectively, by the net stress in thicker T_SOI devices in this CESL strain technology. In addition, the bending extent of gate oxide film of nMOSFETs is larger than that of pMOSFETs due to the larger net stress in gate oxide film resulting from additional compressive stress of shallow trench isolation (STI) pressed on SOI. Therefore, an appropriate SOI thickness design is the key factor to achieve superior device performance and reliability.     

浮栅结构SOI LDMOS 器件的模拟研究

研究了一种具有浮栅结构的SOI LDMOS(FGSOI LDMOS)器件模型,并分析了该结构的耐压机理,通过Silvaco TCAD软件对该结构进行仿真优化。通过仿真验证可知,该结构通过类场板的结终端技术可以调节器件的横向电场,从而得到比普通SOI LDMOS器件更高的耐压并且降低了器件的比导通电阻。仿真结果表明,该结构与普通SOI LDMOS器件结构在相同的尺寸条件下耐压提高了41%,比导通电阻降低了21.9%。     

基于RIE技术的倾斜表面SOI功率器件制备技术

对一种具有倾斜表面漂移区SOI LDMOS的制造方法进行了研究,提出了多窗口反应离子刻蚀法来形成倾斜表面漂移区的新技术,建立了倾斜表面轮廓函数的数学模型,TCAD工具的2D工艺仿真证实了该技术的可行性,最终优化设计出了倾斜表面漂移区长度为15μm的SOI LDMOS.数值仿真结果表明,其最优结构的击穿电压可达350 V...     

An on-engine method for dynamic characterisation of NOx concentration sensors

An on-engine method for dynamic characterisation of automotive NO_x concentration sensors is presented. Steps in start of injection on a diesel engine are employed to achieve step-like NO_x concentration variations on exhaust flow. On the basis of the sensor response, delay and dynamic response can be easily identified; the paper shows a simple least squares procedure although other models and identification techniques could be used. Application data is presented for three NO_x sensors: a research-grade chemiluminescence exhaust gas analyser, and two different commercial ZrO₂-based sensors.     

Microwave photonic filter with a continuously tunable central frequency using an SOI high-Q microdisk resonator

Utilizing a high-Q microdisk resonator(MDR) on a single silicon-on-insulator(SOI) chip, a compact microwave photonic filter(MPF) with a continuously tunable central frequency is proposed and experimentally demonstrated. Assisted by the optical single side-band(OSSB) modulation, the optical frequency response of the MDR is mapped to the microwave frequency response to form an MPF with a continuously tunable central frequency and a narrow 3-dB bandwidth. In the experiment, using an MDR with a compact size of 20×20 μm2and a high Q factor of 1.07×105, we obtain a compact MPF with a high rejection ratio of about 40 dB, a 3-dB bandwidth of about 2 GHz, and a frequency tuning range larger than12 GHz. Our approach may allow the implementation of very compact, low-cost, low-consumption, and integrated notch MPF in a silicon chip.     

Silicon nanowires as field-effect transducers for biosensor development: A review

The unique electronic properties and miniaturized dimensions of silicon nanowires (SiNWs) are attractive for label-free, real-time and sensitive detection of biomolecules. Sensors based on SiNWs operate as field effect transistors (FETs) and can be fabricated either by top–down or bottom–up approaches. Advances in fabrication methods have allowed for the control of physicochemical and electronic properties of SiNWs, providing opportunity for interfacing of SiNW-FET probes with intracellular environments. The Debye screening length is an important consideration that determines the performance and detection limits of SiNW-FET sensors, especially at physiologically relevant conditions of ionic strength (>100 mM). In this review, we discuss the construction and application of SiNW-FET sensors for detection of ions, nucleic acids and protein markers. Advantages and disadvantages of the top–down and bottom–up approaches for synthesis of SiNWs are discussed. An overview of various methods for surface functionalization of SiNWs for immobilization of selective chemistry is provided in the context of impact on the analytical performance of SiNW-FET sensors. In addition to in vitro examples, an overview of the progress of use of SiNW-FET sensors for ex vivo studies is also presented. This review concludes with a discussion of the future prospects of SiNW-FET sensors.