单粒子瞬态脉冲宽度量化与自测试电路设计

为了研究组合逻辑中单粒子瞬态(Single-Event Transient,SET)的特性,采用片上测量技术提出了一套SET脉冲宽度测量方案.针对SET脉冲特性,设计了一种基于自主触发的脉冲测量电路,提出了一种用于自测试验证的脉冲激励电路.基于本所350nm SOI工艺,完成了一款集脉冲收集、测量、自测试于一体的SET重离子辐射测试芯片.通过仿真分析,验证了该方案的有效性.此方案为其他深亚微米工艺下SET研究提供了参考.     

电磁兼容缩尺比测试方法介绍

本文对电磁兼容缩尺比测试方法进行了介绍.该方法适用于大型多天线产品研制过程中的电磁兼容预测试,易于在产品成型之前发现解决其潜在的电磁兼容问题,节约成本,是大型多天线产品研制过程中及其必要的测试手段.     

PLC控制系统可靠性研究

PLC控制系统的可靠性从硬件和软件方面共同衡量。从电源的处理、连接线的方式、冗余设计、控制系统的输入电路和输出电路与PLC的软件程序编制等多个方面,论述了一些可行的方法和措施。     

Single chip bumping and reliability for flip chip processes

Processes of bump deposition based on mechanical procedures together with their reliability data are summarized in this paper. The stud bumping of gold, palladium, and solder is described and also a novel bumping approach for fine pitch solder deposition down to 100 μm pitches using thermosonic bonding on a modified wedge–wedge bonding machine. This wedge bumping doesn’t require a wire flame-off process step. Because of this, no active atmosphere is necessary. The minimum pad diameter which can be bumped using the solder wedge bumping is 50 μm, up to now. This bumping process is highly reproducible and therefore well-suited for different flip chip soldering applications. Palladium stud bumps provide a solderable under bump metallization. Results from aging of lead/tin solder bumps on palladium are shown. The growth of intermetallics and its impact on the mechanical reliability are investigated.     

Via wearout detection with on-chip monitors

This project aims to detect the onset of chip failure due to via voiding through monitoring the delays of paths in a chip. The proposed method relates the probability of failure of individual vias to an increase in delay for monitors of the system using data for 65 nm technology. The delay increase, as a function of the failure distribution parameters, the path length, gate type, and process variation, has been investigated. An on-chip, ring oscillator-based wearout monitoring circuit is presented. The proposed scheme monitors the delay through a data path using a delay detection circuit (DDC).     

Assessment of long term reliability of photovoltaic glass–glass modules vs. glass-back sheet modules subjected to temperature cycles by FE-analysis

Quantifying the reliability of photovoltaic (PV) modules is essential for consistent electrical performance and achieving long operational lifetimes. Optimisation of these parameters increases the profitability of photovoltaic electricity because such systems should only require an initial capital investment. There are several aspects in a PV module which compromise its profitability. One such important aspect is the thermo-mechanical stress that is induced by day to night temperature cycles during every day of operation. Since this stress obviously cannot be omitted the PV module set-up should reduce the resulting internal loads to a minimum. This paper analyses the effects of the thermally induced stresses in two different module constructions.The thermo-mechanical reliability of photovoltaic modules is tested by the IEC standard 61,215 which accelerates the day to night cycles. Detailed analysis of this experimental test method is done by FEM simulations. Results of those numerical analyses are able to directly analyse the internal stresses in a PV module. The investigation presented here applies a classic module assembly for H-patterned cells with a single front glass and a plastic back sheet which is the reference type. The second packaging type for H-patterned PV cells is the glass–glass module which replaces the back sheet by a second glass sheet. Both module types have the same base area including 60 solar cells and the same total thickness.Each of the module assemblies are transferred to 3-D FE-models and subjected to temperature cycles. The simulation results show no module deformation for the symmetrical glass–glass module while the glass-back sheet assembly deforms by several mm. The mechanical results show that the solar cells are displaced towards each other when temperatures decline and vice versa during temperature increase. This forced movement causes stresses and strains in the interconnection structures of the modules. The analyses reveal that inside the glass–glass module the copper ribbons and solder layers are subjected to higher mechanical loads compared to the reference type. In case of the glass–glass module the copper ribbons may fail which can result in a complete cut of the series-connected solar cell strings.     

马氏骨架理论在系统可靠性中的应用

本文利用侯振挺等人提出的马尔可夫骨架过程理论讨论了串——并联混合系统的可靠性.该模型有四个不同部件和一个修理工组成,部件的寿命和修理时间均服从一般分布.     

无失效数据情形可靠性参数的估计和调整

本文在无失效取样情形下,提出了产品可靠性参数的一种估计和调整的方法———加权多层Bayes估计法.在无失效数据情形下失效率的多层Bayes估计和引进失效信息后失效率的多层Bayes估计的基础上,对可靠性参数进行了估计和调整———给出了失效率和可靠度的加权多层Bayes估计.最后,结合发动机的实际问题进行了计算,结果表明本文提出的方法可行且便于应用.     

长寿命产品在小子样缺失数据下的Bayes可靠性增长分析

在长寿命产品的可靠性增长试验过程中,由于人员、观测设备或其他方面的原因,可能会造成某些试验数据丢失或未观测到的现象。对这类小子样变总体缺失数据情形,提出了Bayes可靠性增长分析方法。首先利用Box-Tiao技术构造先验分布,然后利用非齐次Poisson过程原理和缺失数据的产生机制,得到可靠性增长缺失数据的似然函数,再用Bayes统计推断方法得到产品各研制阶段结束时的可靠性水平,同时给出了缺失数据下增长模型的拟合优度检验方法。最后通过一个示例说明了该方法在工程上的应用。     

Reliability evaluation of multi-state systems under cost consideration

A more practical and desirable performance index of multi-state systems is the two-terminal reliability for level (d, c) (2TR_d,c), defined as the probability that d units of flow can be transmitted from the source node to the sink node with the total cost less than or equal to c. In this article, a simple algorithm is developed to calculate 2TR_d,c in terms of (d, c)-MPs. Two major advantages of the proposed algorithm include: (1) as of now, it is the only algorithm that searches for (d, c)-MPs without requiring all minimal paths (MPs) and the procedure of transforming feasible solutions; (2) it is more practical and efficient in solving (d, c)-MP problem in contrast to the best-known method. An example is provided to illustrate the generation of (d, c)-MPs by using the presented algorithm, and 2TR_d,c is thus evaluated. Furthermore, the computational experiments are conducted to verify the performance of the presented algorithm.