Novel Architecture for Efficient Implementation of Dimmable VPPM in VLC Lightings

In this paper, a new architecture is proposed to achieve complexity efficiency in implementing variable pulse position modulation (VPPM). VPPM, specified in IEEE 802.15.7, can support wireless communication and dimming control simultaneously using visible light. The proposed architecture is based on the VPPM signal property in which the transition point of the modulated output is obtained by counting the sample index and comparing it to both the assigned dimming factor and the transmitting data. Therefore, the proposed architecture can be composed of simple logics, including a counter, a comparator, and an inverter, all of which are insensitive to the dimming resolution in contrast to a conventional codeword‐table method. This paper describes the verification of the proposed algorithm through a register‐transfer level implementation of the codeword and proposed architectures. In comparison with the codeword‐table method, the proposed method gains a nine‐fold complexity reduction at a 1% dimming‐step resolution.     

Synthesis of Scan Chains for Netlist Descriptions at RT-Level

This paper presents a methodology to insert scan paths in a functional Register Transfer Level (RTL) specification of a design that can exploit existing functional paths between sequential elements in the original circuit for establishing scan chains. The primary objective for RTL scan insertion is to reduce the time taken for DFT, and thus reduce the time to market. Additionally, building scan chains at the functional RT-Level is expected to reduce the total area overhead introduced by full scan without compromising the fault coverage achieved. In addition, it often eliminates the delay associated with the additional multiplexer as a part of a conventional scan-cell in high performance designs. Experimental results presented in this paper demonstrate that the proposed method achieves the above objectives while also achieving higher fault coverages for most of the benchmark circuits considered.     

基于IPV6的新型检测装置的设计

IPV6在网络通讯,资源共享等多方面比IPV4具有更多的优点.当前大部分检测设备中的通讯的实现仍然是以IPV4为基础,严重地阻碍了下一代互联网的发展,也不利于控制系统的研究.基于IPV6的检测装置的设计,采用80C51系列的单片机控制系统实现数据的采集,用网卡芯片RTL8019AS实现数据传输到互联网上.采用生成代码效率高的单片机C语言完成程序的代码开发,对工业控制系统及下一代互联网的发展有重要的意义.     

Determination of engineered nanoparticles on textiles and in textile wastewaters

Textile materials with engineered nanoparticles (ENPs) have excellent properties as they are antibacterial, antimicrobial, water resistant and protective. The textile industry has recognized the importance and the advantages of ENPs, so they comprise one of the fastest developing branches of processing.The most important sources of ENPs released to the environment from textiles are textile-industry wastewaters and waters from large hospital or hotel laundries. In addition, waste textile materials coated with ENPs present a threat to the environment, if such materials are not properly handled and disposed of after use.Currently, the toxicity and the potential harm of ENPs widely applied on textiles are not thoroughly investigated and/or eliminated. Consequently, there is an urgent need to define the most appropriate analytical methods for monitoring ENPs on textiles.This review presents the most important techniques for monitoring ENPs on textile materials and in textile-wastewater samples, from the perspective of protecting the environment and human health.     

Liquid Chromatorgraphic Separation of the Enantiomers of Phenylthiohydantoin α-Amino Acids Derivatives on Polysaccharide-Based Chiral Stationary Phases

ABSTRACT

The liquid chromatographic enantioseparation of the phenylthiohydantoin (PTH) derivatives of various amino acids on four commercial polysaccharide-derived chiral stationary phases (CSPs) is described. Chiralcel OF and Chiralpak AS showed better performance than the other CSPs for resolution of the enantiomers of PTH amino acid derivatives. The enantiomers of all amino acids as their PTH derivatives were well separated on Chiralcel OF and/or Chiralpak AS. The (-)(L) or (-)-enantiomers of all analytes examined were preferentially retained on Chiralpak AS, whereas the (+)(D) or (+)-enantiomers of most of analytes were preferentially retained on Chiralcel OF.     

采用IMS发展Internet用户的解决方案

文章介绍了一个采用IMS发展Internet用户的解决方案。该方案通过PushAS、重路由、计费等特殊设计,满足Internet用户不同于普通电信用户的组网需求。文章分析了Internet用户的话务模型和业务发展情况,指出Internet用户具有高申请率、低使用率的特点,适合采用Web自助开销户方式、预付费计费方式。IMS网络除了用于固网改造,发展Internet用户也是当前可行的应用方式。     

Towards accelerating irregular EDA applications with GPUs

Recently graphic processing units (GPUs) are rising as a new vehicle for high-performance, general purpose computing. It is attractive to unleash the power of GPU for Electronic Design Automation (EDA) computations to cut the design turn-around time of VLSI systems. EDA algorithms, however, generally depend on irregular data structures such as sparse matrix and graphs, which pose major challenges for efficient GPU implementations. In this paper, we propose high-performance GPU implementations for a set of important irregular EDA computing patterns including sparse matrix, graph algorithms and message-passing algorithms. In the sparse matrix domain, we solve a core problem, sparse-matrix vector product (SMVP). On a wide range of EDA problem instances, our SMVP implementation outperforms all prior work and achieves a speedup up to 50× over the CPU baseline implementation. The GPU based SMVP procedure is applied to successfully accelerate two core EDA computing engines, timing analysis and linear system solution. In the graph algorithm domain, we developed a SMVP based formulation to efficiently solve the breadth-first search (BFS) problem on GPUs. We also developed efficient solutions for two message-passing algorithms, survey propagation (SP) based SAT solution and a register-transfer level (RTL) simulation. Our results prove that GPUs have a strong potential to accelerate EDA computing through designing GPU-friendly algorithms and/or re-organizing computing structures of sequential algorithms.     

智能Mil-1394B总线仿真器的设计和开发

针对市场上缺少1394总线测试仿真设备的现状,文中介绍了Mil-1394总线协议的发展情况,给出了一种基于智能处理器和FPGA为主要构架的Mil-1394总线仿真器的实现方案,重点描述了自主通讯诊断功能和智能协议处理能力的设计思路,并对软硬件设计等方面进行了详细论述,为Mil-1394总线的应用及测试提供了一种新的思路     

A novel direction of arrival estimator

A Direction Of Arrival(DOA) estimator based on the signal separation principle is introduced, and one of representative multidimensional estimators is established by introducing Matrix Operator projection signal steering Vector Excision(MOVE) operation. Thanks to Alternating Separation (AS) technique, the multidimensional problem is transformed into a series of one-dimensional optimal ones. Furthermore, an equivalent simplified implementation of the AS is obtained. Finally the definiteness and uniqueness of the estimator are analyzed.     

基于DSP和TCP/IP的嵌入式网络数据采集系统

提出一种有效的、低成本的嵌入式系统TCP/IP协议栈实现方案.阐述了在TMS320F2407A中实现TCP/IP协议的基本原理.通过对TCP/IP协议进行裁减,采用全汇编语言程序设计方法、灵活的消息控制机制和缓冲区管理,在有限的代码空间内实现了TCP/IP协议栈.