一种规整高效的缩1码模2^n＋1乘法器的VLSI设计

针对目前缩1码模2n＋1乘法器的优缺点,设计出一个有效的缩1码模2n＋1乘法器。该模乘法器是由改进的基-4 Booth编码模块、规整的缩1码进位保留加法器树以及缩1码模加法器构成,部分积的个数减少到n/2＋2个,具有统一的编码电路,简单的校正项生成电路,较快的计算速度,尤其是能够处理操作数和结果为0的情况,实现了操作数的全输入。比较结果表明,该模乘法器在同类型模乘法器中以最少的面积获得了更快的速度。     

基于RNS算法的高阶FIR滤波器设计

以{2n－1,2n,2n+1,2ⁿ－¹－1,2ⁿ⁺¹－1}为余数基,在余数系统(RNS)的基础上设计了一种128抽头有限脉冲响应(FIR)滤波器。针对大位宽输入,利用基于华莱士(Wallace)树结构的纯组合逻辑电路,实现了二进制到余数的转换。相较于一般抽头中乘法器级联加法器的结构,设计的乘累加(MAC)单元将加法运算合并到部分积求和中,减少了一级模加法器,使得电路延时进一步减少。此外,通过对进位保留加法器(CSA)的中间结果取模,避免了加法运算引起的位宽增加,从而降低了整个运算的复杂度。电路在FPGA上设计实现。实验结果表明,该滤波器的延时为3.55 ns,功耗为2 585 mW,消耗的硬件资源明显降低。     

RNS与Delta-Sigma编码的位数据流的数值转换算法及硬件实现

利用RNS(余数数制系统)可以执行并行的数据处理以及实现快速无进位算法,在VLSI(超大规模集成电路)设计中表现出低功耗、占用面积小和时延少等优良特性.根据中国剩余定理,基于(2n-1)2n(2n+1)模组,利用Verilog语言设计了RNS到位数据流的数值转换接口电路.以使传统的多位数(Bit)的复杂运算转化为多个并行的较少位数的简单运算,从而降低单次运算的复杂度、时延和功耗.该转换电路面向"Σ-Δ"编码的数据流,不同于传统的二进制数据转换,可以方便地与基于DSD(Direct Stream Digital)的Delta-Sigma系统进行无缝连接.     

Novel digital filter implementations using hybrid RNS-binary arithmetic

The implementation of a FIR filter using a new hybrid RNS-binary arithmetic is presented for the first time. In the new arithmetic, the data samples are represented using RNS, and hence the carry free advantage of RNS computations is retained. However, the computation performed for each modulo is implemented using conventional binary arithmetic elements which overcome the drawback of ROM-based RNS arithmetic elements that become inefficient for large moduli. The conventional binary arithmetic elements are also faster and require less area than existing memoryless RNS arithmetic elements. It is shown that the filter structures based on the new arithmetic have better performance than those based on either the conventional binary or conventional RNS arithmetic for large moduli.     

Electrochemical sensors for oxidative stress monitoring

Electrochemical sensors are ideally suited for the detection of reactive oxygen and nitrogen species (ROS and RNS) generated during biological processes. This review discusses the latest work in the development of electrochemical microsensors for ROS/RNS and their applications for monitoring oxidative stress in biological systems. The performance of recent designs of microelectrodes and electrode materials is discussed along with their functionality in preclinical models of drug efficacy, mitochondrial distress, and endothelial dysfunction. Challenges and opportunities in translating this methodology to study the pathophysiology associated with various diseases are discussed.     

余数系统在软件无线电中的应用

余数系统由于其良好的并行特性,在乘加密集型的数字信号处理系统中得到了广泛关注,而这正是构建软件无线电系统的关键所在.本文在介绍RNS基本理论的基础上,结合已有的研究成果.指出了基于RNS的数字信号处理系统关键单元及研究现状,并提出了一种基于RNS数值表征系统的DSP系统结构.结合冗余RNS的容错特性和并行性,介绍了一种基于RNS的多路并行正交通信系统,并指出了其在阵列SDR平台和航天级SDR平台设计中的应用.可以预见,在构建未来复杂SDR系统中,RNS将得到广泛应用.     

Incremental Redundancy and Link Adaptation in Wireless Local Area Networks Using Residue Number Systems

The paper explores the use of residue number systems (RNS) to incorporate incremental redundancy (IR) and link adaptation (LA) in wireless communication systems. This also explores the use of RNS to increase the transmission data rate and to enhance the privacy of a wireless network. By exploiting IR and LA further, one can design an appropriate coding scheme for transmission at the currently experienced SNR level. The proposed method is implemented in existing wireless local area network (WLAN) standards and simulated extensively to find its suitability. The results of simulation studies are discussed in details.     

Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic

Field-programmable logic (FPL), often grouped under the popular name field-programmable gate arrays (FPGA), are on the verge of revolutionizing sectors of digital signal processing (DSP) industry as programmable DSP microprocessor did nearly two decades ago. Historically, FPGAs were considered to be only a rapid prototyping and low-volume production technology. FPGAs are now attempting to move into the mainstream DSP as their density and performance envelope steadily improve. While evidence now supports the claim that FPGAs can accelerate selected low-end DSP applications (e.g., FIR filter), the technology remains limited in its ability to realize high-end DSP solutions. This is due primarily to systemic weaknesses in FPGA-facilitated arithmetic processing. It will be shown that in such cases, the residue number system (RNS) can become an enabling technology for realizing embedded high-end FPGA-centric DSP solutions. This thesis is developed in the context of a demonstrated RNS/FPGA synergy and the application of the new technology to communication signal processing.     

基于余数系统与置换多项式的高速长周期伪随机序列生成方法

低复杂度长周期数字伪随机序列在现代加密、通信等系统中具有广泛的应用。该文提出一种基于余数系统和有限域置换多项式的伪随机序列生成方法。该方法基于中国剩余定理将多个互质的小周期有限域随机序列进行单射扩展生成长周期数字伪随机序列,置换多项式的迭代计算在多个并行的小动态范围有限域上进行,从而降低了硬件实现中迭代环路的计算位宽,提高了生成速率。该文还给出构建长周期伪随机序列的置换多项式参数选择方法和中国剩余定理优化方法,在现有技术平台下可轻易实现2100以上的序列周期。同时,该方法具有极大的迭代多项式选择自由度,例如仅在q2(mod)3且q503的有限域上满足要求的置换多项式就有10905种。硬件实现结构简单,基于Xilinx XC7Z020芯片实现290的随机序列仅需20个18 kbit的BRAM和少量逻辑资源,无需乘法器,生成速率可达449.236 Mbps。基于NIST的测试表明序列具有良好的随机特性。