Assessing the width of Gaussian density of states in organic semiconductors

The Density of States (DOS) is an ingredient of critical importance for the accurate physical understanding of the optoelectronic properties of organic semiconductors. The disordered nature of this class of materials, though, renders the task of determining the DOS far from trivial. Its extraction from experimental measurements is often performed by driving the semiconductor out of thermal equilibrium and therefore requires making assumptions on the charge transport properties of the material under examination. This entanglement of DOS and charge transport models is unfavorable since transport mechanisms in organic semiconductors are themselves still subject of debate. To avoid this, we propose an alternative approach which is based on populating and probing the DOS by means of capacitive coupling in Metal Insulator Semiconductors (MIS) structures while keeping the semiconductor in thermal equilibrium. Assuming a Gaussian shape, we extract the DOS width by numerical fitting of experimental Capacitance–Voltage curves, exploiting the fact that the DOS width affects the spatial distribution of accumulated charge carriers which in turn concurs to define the MIS capacitance. The proposed approach is successfully tested on two benchmark semiconducting polymers, one of n-type and one of p-type and it is validated by verifying the robustness of the extraction procedure with respect to varying the insulator electrical permittivity. Finally, as an example of the usefulness and effectiveness of our approach, we study the static characteristics of thin film transistors based on the aforementioned polymers in the framework of the Extended Gaussian Disorder transport model. Thanks to the extracted DOS widths, the functional dependence of current on the gate voltage is nicely predicted and physical insight on transistor operation is achieved.     

Investigation of geometry dependence on MOSFET linearity in the impact ionization region using Volterra series

In this paper, investigation of device geometry on intermodulation distortion (IMD) of metal–oxide–semiconductor field-effect transistors (MOSFETs) is presented in the impact ionization region based on the Volterra analysis. As the gate length or gate width decreases, observed linearity improvement of the MOSFET in the breakdown regime is attributed to the more obvious breakdown inductance nonlinearity which cancels the transconductance nonlinearity. Linearity of the MOSFETs can be improved by choosing suitable device geometry in the breakdown region. It is believed the presented analysis results can benefit the reliability investigation for MOSFET linearity in the breakdown region.     

基于有序介孔碳的氯离子选择性电极的制备及其在手持传感系统中的应用

以有序介孔碳(OMC)球为离子-电子转换层,制备了固态氯离子选择性电极,构建了基于离子敏感的场效应晶体管(ISFET)的手持式传感系统,用于检测人体血清中的氯离子。优化了OMC前驱体的碳化温度,探究了OMC形貌结构对电极传感性能的影响;电极柔性化制备后考察了其在手持系统中对氯离子的检测效果。结果表明,最优条件下,电极在5.12×10^-4~1.02 mol/L的浓度范围呈现线性响应,响应斜率为60 mV/decade。该柔性电极在手持传感系统中展现出高灵敏度和重现性,可用于人体血清样品中氯离子的检测,其回收率为96.3%~104.9%。     

Monolithic integration of an AlGaN/GaN metalinsulator field-effect transistor with an ultra-low voltage-drop diode for self-protection

In this paper,we present a monolithic integration of a self-protected AlGaN/GaN metal-insulator field-effect transistor(MISFET).An integrated field-controlled diode on the drain side of the AlGaN/GaN MISFET features a selfprotected function for a reverse bias.This diode takes advantage of the recessed-barrier enhancement-mode technique to realize an ultra-low voltage drop and a low turn-ON voltage.In the smart monolithic integration,this integrated diode can block a reverse bias(> 70 V/μm) and suppress the leakage current(< 5 × 10-11 A/mm).Compared with conventional monolithic integration,the numerical results show that the MISFET integrated with a field-controlled diode leads to a good performance for smart power integration.And the power loss is lower than 50% in conduction without forward current degeneration.     

Subtle gate oxide defect elimination to improve the reliability of a 32M-bit SRAM product

Tiny defects may escape from in-line defect scan and pass WAT (Wafer Acceptance Test), CP (Chip Probing), FT (Final Test) and SLT (System Level Test). Chips with such kind of defects will cause reliability problem and impact revenue significantly. It is important to catch the defects and derive the prevention strategy earlier in the technology development stage. In this paper, we investigate an SRAM with tiny defects which passed in-line defect scan, WAT, CP and FT but failed in HTOL (High Temperature Operation Life) test, one of the product reliability qualification items. FA (Failure Analysis) reveals gate oxide missing defect is the root cause. The goal is to pass reliability qualification and release product into production on schedule. The failure mechanism, optimization of gate oxide process, enhancement of defect scan and testing methodology will be introduced. Experiment results show very good HTOL performance by the combination of process and testing optimization.     

Fabrication of a planar water gated organic field effect transistor using a hydrophilic polythiophene for improved digital inverter performance

A planar water gated OFET (WG-OFET) structure is fabricated by patterning gate, source and drain electrodes on the same plane at the same time. Transistor output characteristics of this novel structure employing commercial regioregular poly(3-hexylthiophene) (rr-P3HT) as polymer semiconductor and deionized (DI) water as gate dielectric show successful field effect transistor operation with an on–off current ratio of 43 A/A and transconductance of 2.5 μA/V. These output characteristics are improved using P3HT functionalized with poly(ethylene glycol) (PEG) (P3HT-co-P3PEGT), which is more hydrophilic, leading to on–off ratio of 130 A/A and transconductance of 3.9 μA/V. Utilization of 100 mM NaCl solution instead of DI water significantly increases the on–off ratio to 141 A/A and transconductance to 7.17 μA/V for commercial P3HT and to 217 A/A and to 11.9 μA/V for P3HT-co-P3PEGT. Finally, transistors with improved transconductances are used to build digital inverters with improved characteristics. Gain of the inverters employing P3HT and P3HT-co-P3PEGT are measured as 2.9 V/V and 10.3 V/V, respectively, with 100 mM NaCl solution.     

Accounting for variability in the design of circuits with organic thin-film transistors

We experimentally verify that the methodology to account for local parameter variations and transistor mismatch known in Si CMOS technologies can be transposed to organic thin-film transistor technologies, and we present a design case that makes use of design for variability. Transistor parameter variation decreases with the square root of the transistor footprint. As a consequence, Monte Carlo simulations which take this effect into account can be executed to better predict the final circuit yield. The design case in this work is an 8-bit, organic RFID transponder chip. The yield prediction by simulations corresponds to the finally observed circuit yield.     

Carboxylic acid mediated self-assembly of small molecules for organic thin film transistors

A p-type small molecule bearing dicarboxylic acid functional group (–COOH) is synthesized and evaluated for field-effect transistor properties. We discover and report for the first time, that the –COOH groups assist in the passivation of surface traps on the dielectric layer and simultaneously facilitate the self-assembly of the molecules via inter-molecular hydrogen bonding resulting in crystalline active channels. A 9-fold decrease in the threshold voltage was observed for the transistors made using the –COOH functionalized molecule, QT-DA, compared to its ester analogue, QT-ES, providing an evidence of surface passivation. This resulted in an increase in the hole mobility of QT-DA by up to 2 orders of magnitude. It was shown that QT-DA adopts a vertical alignment with respect to the substrate due to preferential interaction between the –COOH groups and the SiO₂ surfaces.     

雪崩击穿条件下4.5kV IGBT器件的背面优化研究

The static avalanche breakdown behavior of 4.5 kV high-voltage IGBT is studied by theory analysis and experiment. The avalanche breakdown behaviors of the 4.5 kV IGBTs with different backside structures are investigated and compared by using the curve tracer. The results show that the snap back behavior of the breakdown waveform is related to the bipolar PNP gain, which leads to the deterioration of the breakdown voltage. There are two ways to optimize the backside structure, one is increasing the implant dose of the N C buffer layer, the other is decreasing the implant dose of the P C collector layer. It is found that the optimized structure is effective in suppressing the snap back behavior and improving the breakdown characteristic of high voltage IGBT.     

The impact of gate misalignment on the analog performance of a dual-material double gate junctionless transistor

The analog performance of gate misaligned dual material double gate junctionless transistor is demonstrated for the first time. The cases considered are where misalignment occurs towards source side and towards drain side. The analog performance parameters analyzed are: transconductance, output conductance, intrinsic gain and cut-off frequency. These figures of merits (FOMs) are compared with a dual material double gate inversion mode transistor under same gate misalignment condition. The impacts of different length of control gate (L₁) for a given gate length (L) are also studied and the optimum lengths L₁ under misalignment condition to have better analog FOMs and high tolerance to misalignment are presented.