一种新的磷化铟复合沟道高电子迁移率晶体管小信号物理模型

针对磷化铟(InP)复合沟道高电子迁移率晶体管(HEMT)的特点，对常规单沟道HEMT的小信号物理模型进行了修正，提出了一种新的用于复合沟道HEMT的小信号物理模型，用商用器件模拟软件ISE(integrated systems engineering)对其进行了仿真验证，对比了实测和仿真的I-V特性及转移特性曲线，重点研究了在InGaAs/InP双层沟道中考虑量子效应后的电场和电流密度随着不同栅电压的变化趋势，研究结果表明，由于在沟道中存在量子效应，在栅下靠源端低电场区域，电流主要分布在InGaAs沟道 关键词： 高电子迁移率晶体管 复合沟道 物理模型 磷化铟     

MOS功率驱动高速脉冲激光器的研究

运用经典电路理论,对MOS功率管的开关特性、驱动原理进行了分析,导出了应用MOS功率管实现高速大电流开关应遵从的原则和方法,并成功地实现了光脉冲上升时间小于5ns、下降时间小于10ns,驱动电流达10～50AP-P激光器电源的要求.     

Correlated and non-correlated growth kinetics of pentacene in the sub-monolayer regime

We present a study of the growth kinetics of pentacene monolayer islands on SiO₂ in the submonolayer regime by using Atomic Force Microscopy (AFM). Two distinct growth modes, namely correlated growth (CG) and non-correlated growth (NCG), have been identified by Voronoi tesselation. These two modes are characterized by different island growth kinetics. In the case of correlated growth, the average island size 〈A〉 scales with deposition time t i.e. 〈A〉 ∝ t whereas for non-correlated growth, 〈A〉 ∝ t². The CG and NCG regimes are defined by the level of re-evaporation which determines the capture zones around the islands: Wigner-Seitz cells for CG and coronas of width λ_D (λ_D is the mean diffusion distance on SiO₂ before re-evaporation) for NCG. A simple model is proposed to reproduce the experimental growth kinetics in both modes.     

High-k材料MOS器件的PISCES-II模拟

High-k材料是指介电常数k高于SiO2的材料。使用high-k材料做栅绝缘层,是减小MOS器件栅绝缘层直接隧道击穿(DirectTunneling,DT)电流的有效方法。文章在二维器件模拟软件PISCES-II中添加了模拟以high-k材料为栅绝缘层的MOS器件模型,并对SiO2和high-k材料的MOS晶体管器件特性进行了模拟比较,成功地验证了所加high-k材料MOS器件模型的正确性。改进后的PISCES-II程序,可以方便地对以各种high-k材料为栅绝缘层的器件性能进行模拟。     

SiGe (Ge-dot) heterojunction phototransistors for efficient light detection at 1.3–1.55 μm

The aim of this work is to develop a Si/SiGe HBT-type phototransistor with several Ge dot layers incorporated in the collector, in order to obtain improved light detectivity at 1.3–1.55 μm. The MBE grown HBT detectors are of n–p–n type and based on a multilayer structure containing 10 Ge-dot layers (8 ML in each layer, separated by 60 nm Si spacer) in the base-collector junction. The transistors were processed for normal incidence or with waveguide geometry where the light is coupled through the edge of the sample. The measured breakdown voltage, BV_ceo, was about 6 V. Compared to a p–i–n reference photodiode with the same dot layer structure, photoconductivity measurements show that the responsivity is improved by a factor of 60 for normal incidence at 1.3 μm. When the light is coupled through the edge of the device, the detectivity is even further enhanced. The measured photo-responsivity is more than 100 and 5 mA/W at 1.3 and 1.55 μm, respectively.     

Application of enzyme-field effect transistor sensor arrays as detectors in a flow-injection analysis system for simultaneous monitoring of medium components. Part II. Monitoring of cultivation processes

Glucose, maltose, sucrose, lactose, ethanol and urea concentrations were monitored simultaneously during the cultivation of Escherichia coli and Saccharomyces cerevisiae by means of enzyme field effect transistors (EnFETs) applying glucose dehydrogenase (GDH), maltase (MAL)/GDH, invertase (INV)/GDH, β-galactosidase (β-GAL)/galactosedehydrogenase (GALDH), alcoholdehydrogenase (ADH)/aldehydedehydrogenase (ALDH), and urease. These enzymes were (co)immobilized on the pH sensitive gates of an eight-FET array. The FET array was integrated in a commercial FIA system.     

Shorts in self-checking circuits

It has been noted by several authors that the classical stuck-at logical fault model might not be an appropriate representation of certain real failures occurring in integrated circuits. Shorts are an important class of such faults. This article gives a detailed analysis of the effects of shorts in self-checking circuits and proposes techniques for dealing with them. More precisely, we show that, unlike other faults such as stuck-at, stuck-on, and stuck-open—which produce only single errors in the place they occur—shorts can produce double errors on the two shorted lines. In particular, feedback shorts can produce double errors on the two shorted lines. The double error is unidirectional for some feedback shorts and non-unidirectional for some others. Furthermore, in some technologies (e.g., CMOS), non-feedback shorts can also produce double non-unidirectional errors. We also show that unlike stuck-at, stuck-on, and stuck-open faults, redundant shorts can destroy the SFS property. Then we propose several techniques for coping with these problems and we illustrate the results by circuit implementation examples.The present study is given for NMOS and CMOS circuits but we show that it is valid for any other technology.     

TFT有源矩阵α－Si∶H薄膜PECVD淀积工艺研究

分析了α－Ｓｉ∶Ｈ薄膜的质量和厚度对α－Ｓｉ∶ＨＴＦＴ关键性指标的影响，深入、详细地讨论了其ＰＥＣＶＤ淀积工艺，并在实验的基础上确定了最佳淀积工艺参数，从而获得了高性能的７５ｍｍ３７２×２７６像素α－Ｓｉ∶ＨＴＦＴ有源矩阵     

单电子晶体管电导振荡及其解释

文中概述了单电子晶体管电导振荡的特点并进行了理论解释，进而讨论了介观电容及电容谱的概念。     

单晶硅化物及其应用

本文评述了单晶CoSi_2和NiSi_2的结构特点、各种制备方法、器件应用和发展前景。采用分子束外延(MBE)和“内延”法(Mesotaxy)制备的单晶硅化物质量,电学性能和热稳定性较好。由于首次得到理想的突变的金属——半导体接触,使对金属——半导体接触的理论分析成为可能。硅/单晶硅化物/硅结构在实际应用中非常重要,如单晶硅化物作集电极埋层,能降低集电极串联电阻,克服重掺杂埋层的横扩和自掺杂问题,提高了电路工作速度,减小了器件面积。埋层硅化物也可作为微波传输线的地线,是实现高频集成电路互连的好方法。而采用该结构制备的高速器件——金属基区晶体管(MBT)和穿透基区晶体管(PBT),具有很好的应用前景。