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51.
We have investigated the generation of the 40-GHz double-sideband optical millimeter (mm)-wave with signal carried only by its optical carrier via an embedded LiNbO3 Mach-Zehnder modulator (LN-MZM). Since the optical carrier and its two first-order sidebands are dominant and their powers are well balanced, the first-order harmonic in the photocurrent gets maximal. As the optical mm-wave signal is transmitted along the fiber, there is no code outline distortion because the signal is only modulated on the optical carrier. Although the first-order harmonic shows the periodical fading effect when the optical mm-wave signal is transmitted along the fiber, its degradation on the radio-over-fiber link can be avoided by adjusting the position of the fading nodes via varying the main MZM bias voltage, and the signal still keeps much good eye diagram even after 50-km fiber transmission. The experimental results prove our theory.  相似文献   
52.
本文着重论述了德国BECKHOFF新一代嵌入式PC的新特点,以及在风电变流器中的应用。  相似文献   
53.
简单阐述了当今高技术战争对雷达数据处理系统的要求,叙述了嵌入式计算机、计算机网络、嵌入式实时操作系统和COTS技术在现代雷达设计中的必要性.并就雷达实时数据处理较为关心的嵌入分布式网络体系结构、嵌入式实时操作系统、TCP/IP网络通信、并行模块设计原则、进程间通信、进程调度方式等进行了探讨,详细介绍了基于嵌入式计算机和网络技术的雷达系统软件的设计.对应用该技术前后系统的硬件结构、软件结构、系统的可扩展性、可维修性作了对比。  相似文献   
54.
机器学习势由于具有与第一性原理计算相当的准确性,且低得多的计算成本,在原子模拟中极具前景. 然而原子机器学习势的可靠性、速度和可迁移性在很大程度上取决于原子构型的表示. 适当地选取用作机器学习程序输入的描述符是一个成功的机器学习表示的关键. 本文发展了一种简单有效的方法,可以基于训练数据固有的相关性,从大量待选的描述符中自动选取一组最佳的线性独立原子特征. 通过对几个具有较少冗余线性独立嵌入密度描述符的基准分子构建嵌入原子神经网络势的应用,证明了这种新方法的有效性和准确性. 该算法可以大大简化原子特征的初始选取,并极大地提高原子机器学习势的性能.  相似文献   
55.
本文中应用Credence公司的Gemini500测试系统对某一SoC芯片内嵌模数转换器进行了测试。根据芯片功能分析和封装形式,对测试板进行了优化设计。根据内嵌式ADC的时序特点进行了测试向量的设计。  相似文献   
56.
首先介绍嵌入式UICC(eUICC)的提出背景,总结GSMA、ETSI、3GPP和3GPP2中的相关工作。其中ETSI SCP的研究侧重从卡的角度定义嵌入式UICC的应用场景和需求,3GPP的研究侧重用于3GPP网路的嵌入式UICC参数集、远程配置和更新机制、安全策略等,3GPP2则研究嵌入式UICC在3GPP2网络中的应用需求和远程配置/更新机制。最后对eUICC中的关键技术远程配置管理进行探讨,并提出一种嵌入式UICC远程管理实现方案。  相似文献   
57.
Progressive meshes transmission over a wired-to-wireless network   总被引:1,自引:0,他引:1  
The evolution of mobile network and the popularization of mobile devices; the demand for multimedia services and 3D graphics applications on limited resource devices is more contemporary. Most of the works on multimedia transmission are focused on bit errors and packet losses due to the fading channel environment of a wireless network. Error resilient multimedia is significant research topic which can be adapted to the different conditions in a wireless environment. The current solutions in transmission of multimedia across different networks include some type of transcoder where the source is partially or fully decoded, and re-encoded to suit the network conditions. This paper introduces a flexible progressive coding framework for 3D meshes, which can be adapted to the different conditions imposed by wired and wireless channels at the bitstream level. By avoiding the computationally complex steps of transcoding between networks, could deteriorate decoded model quality. The framework also allows refined degradation of model quality when the network conditions are poor due to congestion or deep fades. Xiaonan Luo, male, born in Feb. 1963 in Jiangxi Province, China, Ph. D., completed his post-doctorate training in Mar. 1995. He is a professor and Ph. D. advisor of the School of Information Science and Technology, and the Chairman of Computer Application Institute of Sun Yat-sen University. His current interests are in mobile graphics transmission and 3D geometric simulation methods. He enjoys the government special allowance granted by the State Council of China. He won the National Science & Technology Progress Prize awarded by the Ministry of Science and Technology of China and the National Natural Science Funds granted by the National Nature Science Foundation of China. Guifeng Zheng, male, born in Jan. 1977 in Guangdong Province, China, Ph. D., received his Ph.D. degree from Sun Yat-sen University in 2005. He is currently an research assistant in the Computer Application Institute of Sun Yat-sen University. His research interests span the areas of wireless networks and mobile graphics computing.  相似文献   
58.
王守磊 《电视技术》2012,36(15):133-137
将手势识别算法在DSP嵌入式系统上实现,并将算法进行改进使其能适合嵌入式系统的特点,采用改进的边缘像素直方图的方法实现手势识别,最终用Bhattacharyya距离匹配模版,识别手势含义。该方法在嵌入式系统上实现,有实际应用的价值,并对前景的平移和尺寸变化不敏感。算法简单快速,稳健性好,有应用前景。  相似文献   
59.
开发具有低功耗、微内核、体积小,并且具有下载功能的嵌入式系统,是非常具有商业价值的。BitTorrent系统是P2P文件共享技术中应用较为广泛的一种,本文在分析通用的BitTorrent软件基础上,给出一种适合嵌入式系统的BitTorrent下载模型,并通过编码在嵌入式Linux之上实现了稳定快速的下载。  相似文献   
60.
Heterogeneous reconfigurable systems provide drastically higher performance and lower power consumption than traditional CPU-centric systems. Moreover, they do it at much lower costs and shorter times to market than non-reconfigurable hardware solutions. They also provide the flexibility that is often required for the engineering of modern robust and adaptive systems. Due to their heterogeneity, flexibility and potential for highly optimized application-specific instantiation, reconfigurable systems are adequate for a very broad class of applications across different industry sectors. What prevents the reconfigurable system paradigm from a broad proliferation is the lack of adequate development methodologies and electronics design tools for this kind of systems. The ideal would be a seamless compilation of a high-level computation process specification into an optimized mixture of machine code executed on traditional CPU-centric processors and on the application-specific decentralized parallel data-flow-dominated reconfigurable processors and hardware accelerators. Although much research and development in this direction was recently performed, the adequate methodologies and tools necessary to implement this compilation process as an effective and efficient hardware/software co-synthesis flow are unfortunately not yet in place. This paper focuses on the recent developments and development trends in the design methods and synthesis tools for reconfigurable systems. Reconfigurable system synthesis performs two basic tasks: system structure construction and application process mapping on the structure. It is thus more complex than standard (multi-)processor-based system synthesis for software-programmable systems that only involves application mapping. The system structure construction may involve the macro-architecture synthesis, the micro-architecture synthesis, and the actual hardware synthesis. Also, the application process mapping can be more complicated and dynamic in reconfigurable systems. This paper reviews the recent methods and tools for the macro- and micro-architecture synthesis, and for the application mapping of reconfigurable systems. It puts much attention to the relevant and currently hot topic of (re-)configurable application-specific instruction set processors (ASIP) synthesis, and specifically, ASIP instruction set extension. It also discusses the methods and tools for reconfigurable systems involving CPU-centric processors collaborating with reconfigurable hardware sub-systems, for which the main problem is to decide which computation processes should be implemented in software and which in hardware, but the hardware/software partitioning has to account for the hardware sharing by different computation processes and for the reconfiguration processes. The reconfigurable system area is a very promising, but quite a new field, with many open research and development topics. The paper reviews some of the future trends in the reconfigurable system development methods and tools. Finally, the discussion of the paper is summarized and concluded.  相似文献   
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