基于DES密码电路的差分功耗分析仿真研究

差分功耗分析技术是目前应用广泛、技术发展较成熟的非侵入攻击技术,设计了一个功耗分析仿真平台,该平台具有自动化程度高、精度高和仿真速度快的特点.此外,还基于该平台实现了对DES密码电路的差分功耗分析,对数字电视机项盒安全性的提高具有参考意义.     

科学改造无功补偿装置减少电费支出

分析了功率因数偏低的原因,主要原因有原有低压无功补偿装置设计不合理,器件出现故障,不能提供系统所需的无功补偿功率。通过实例给出了无功补偿装置改造的具体做法,如加装电抗器,选用耐压等级合适的电容器,采用无功补偿装置专用交流接触器,并合理规划了无功补偿柜内散热通道。最后对改造前后的经济效益进行了分析。     

片上电磁干扰感应阵列的设计与FPGA验证

测量EMI在片上电源分配网络中的二维分布,对研究集成电路的电磁抗扰性非常重要,能用于验证电磁抗扰模型的正确性。提出的片上电磁干扰感应阵列(OCEMISA)是一种测量EMI在电源分配网络上二维分布的测量方法。OCEMISA包含数个感应单元,在电源分配网络上产生开关噪声作为反馈信号,其频率各不相等,且只受局部电源电压的影响。用频谱分析仪经由电源引脚探测反馈信号,观察其特征频率随EMI的变化,计算感应单元所在位置EMI的电压分量,并采用FPGA验证OCEMISA的基本功能。     

8位高速低功耗流水线型ADC的设计技术研究

采用7级子ADC流水线结构设计了一个8位80MS/s的低功耗模数转换电路。为减小整个ADC的芯片面积和功耗,改善其谐波失真和噪声特性,重点考虑了第一级子ADC中MDAC的设计,将整个ADC的采样保持电路集成在第一级子ADC的MDAC中,并且采用逐级缩放技术设计7级子ADC的电路结构,在版图设计中考虑每一级子ADC中的电容及放大器的对称性。采用0.18μm CMOS工艺,该ADC的信噪比（SNR）为53dB,有效位数（ENOB）为7.98位,该ADC的芯片面积只有0.56mm2,典型的功耗电流仅为22mA。整个ADC性能达到设计要求。     

12位逐次逼近模数转换器关键设计技术研究

采用逐次逼近方式设计了一个12位的超低功耗模数转换电路。为减小整个ADC的芯片面积、功耗和误差,提高有效位数,对整个ADC的采样保持电路结构进行了精确的设计,重点考虑了其中的高精度比较器电路结构;对以上两个模块的版图设计进行了精细的布局。采用0.18μmCMOS工艺,该ADC的信噪比（SNR）为72dB,有效位数（ENOB）为11.7位,该ADC的芯片面积只有0.36mm2,典型的功耗仅为40μW,微分非线性误差DNL小到0.6LSB、积分非线性误差INL只有0.63LSB。整个ADC性能达到设计要求。     

一种可靠、高效、灵活的数据中心机房供电解决方案

随着中国移动数据业务迅速发展,中国移动各地数据机房将陆续建设,如何合理设置机房供电系统,对节能、节地都起着至关重要的作用。本文结合新技术的应用,提出了一种靠、高效、灵活的数据中心机房供电解决方案。     

Improving the performance of packet-switched networks-on-chip by SDM-based adaptive shortcut paths

Reducing the NoC power is critical for scaling up the number of nodes in future many-core systems. Most NoC designs adopt packet-switching to benefit from its high throughput and excellent scalability. These benefits, however, come at the price of the power consumption and latency overheads of routers. Circuit-switching, on the other hand, enjoys a significant reduction in power and latency of communication by directing data over pre-established circuits, but the relatively large circuit setup time and low resource utilization of this switching mechanism is often prohibitive. In this paper, we address one of the major problems of circuit-switching, i.e. the circuit setup time overhead, by an efficient and fast algorithm based on the time-division multiplexing (TDM) scheme. We then further improve the performance by reserving circuits for anticipated messages, and hence completely hide circuit setup time. To address the low resource utilization problem, we integrate the proposed circuit-switching into a packet switched NoC and use unused circuit resources to transfer packet-switched data. Evaluation results show considerable reduction in NoC power consumption and packet latency.     

Quantifying the effect of local interconnects on on-chip power distribution

Existing methods to analyze and optimize on-chip power distribution networks typically focus only on global power network modeled as a two-dimensional mesh. In practice, current is supplied to switching transistors through a local power network at the lower metal layers. The local power network is connected to a global network through a stack of vias. The effect of these vias and the resistance of the local power network are typically ignored when optimizing a power network and placing decoupling capacitors. By modeling the power distribution network as a three-dimensional mesh, the error due to ignoring via and local interconnect resistances is quantified. It is demonstrated that ignoring the local power network and vias can both underestimate (by up to 45%) or overestimate (by up to 50%) the effective resistance of a power distribution network. The error depends upon multiple parameters such as the width of local and global power lines and via resistance. A design space is also generated to indicate the valid width of local and global power lines where the target resistance is satisfied. It is shown that a wider global network can be used to obtain a narrower local network, providing additional flexibility in the physical design process since routability is an important concern at lower metal layers. At high via resistances, however, this approach causes significant increase in the width of a global power network, indicating the growing significance of local power network and vias.     

Sintered silver finite element modelling and reliability based design optimisation in power electronic module

This paper discusses the design for reliability of a sintered silver structure in a power electronic module based on the computational approach that composed of high fidelity analysis, reduced order modelling, numerical risk analysis, and optimisation. The methodology was demonstrated on sintered silver interconnect sandwiched between silicon carbide chip and copper substrate in a power electronic module. In particular, sintered silver reliability due to thermal fatigue material degradation is one of the main concerns. Thermo-mechanical behaviour of the power module sintered silver joint structure is simulated by finite element analysis for cyclic temperature loading profile in order to capture the strain distribution. The discussion was on methods for approximate reduced order modelling based on interpolation techniques using Kriging and radial basis functions. The reduced order modelling approach uses prediction data for the thermo-mechanical behaviour. The fatigue lifetime of the sintered silver interconnect and the warpage of the interconnect layer was particular interest in this study. The reduced order models were used for the analysis of the effect of design uncertainties on the reliability of the sintered silver layer. To assess the effect of uncertain design data, a method for estimating the variation of reliability related metrics namely Latin Hypercube sampling was utilised. The product capability indices are evaluated from the distributions fitted to the histogram resulting from Latin Hypercube sampling technique. A reliability based design optimisation was demonstrated using Particle Swarm Optimisation algorithm for constraint optimisation task consists of optimising two different characteristic performance metrics such as the thermo-mechanical plastic strain accumulation per cycle on the sintered layer and the thermally induced warpage.