Low Voltage Class AB Output Stage for CMOS Op-Amps Using Multiple Input Floating Gate Transistors

A new class AB output stage for CMOS op-amps is proposed with simple and accurate quiescent current control using floating gate transistors. The proposed stage can be operated with a supply voltage close to a transistor's threshold voltage. Experimental results are provided showing a 15 MHz gain-bandwidth product when it is used as the second stage of an op-amp with 1.5 V supply voltage in a standard 0.8 m CMOS technology.     

薄膜法布里-珀罗滤光片中反射高斯光束分裂现象

提出了一种模拟薄膜法布里-珀罗滤光片中反射光束分裂现象的方法.根据反射率曲线，简单解释了产生这个现象的原因.实验上制备了薄膜法布里-珀罗滤光片，观察和测量了反射光束分裂的现象，理论计算基本与实验结果符合. 关键词： 薄膜 法布里-珀罗 光束分裂     

InAlSb/InAs/AlGaSb Quantum Well Heterostructures for High-Electron-Mobility Transistors

Heterostructures for InAs-channel high-electron-mobility transistors (HEMTs) were investigated. Reactive AlSb buffer and barrier layers were replaced by more stable Al_0.7Ga_0.3Sb and In_0.2Al_0.8Sb alloys. The distance between the gate and the channel was reduced to 7–13 nm to allow good aspect ratios for very short gate lengths. In addition, n⁺-InAs caps were successfully deposited on the In_0.2Al_0.8Sb upper barrier allowing for low sheet resistance with relatively low sheet carrier density in the channel. These advances are expected to result in InAs-channel HEMTs with enhanced microwave performance and better reliability.     

Low‐Operating‐Voltage Organic Transistors Made of Bifunctional Self‐Assembled Monolayers

Self‐assembled monolayers (SAMs) are molecular assemblies that spontaneously form on an appropriate substrate dipped into a solution of an active surfactant in an organic solvent. Organic field‐effect transistors are described, built on an SAM made of bifunctional molecules comprising a short alkyl chain linked to an oligothiophene moiety that acts as the active semiconductor. The SAM is deposited on a thin oxide layer (alumina or silica) that serves as a gate insulator. Platinum–titanium source and drain electrodes (either top‐ or bottom‐contact configuration) are patterned by using electron‐beam (e‐beam) lithography, with a channel length ranging between 20 and 1000 nm. In most cases, ill‐defined current–voltage (I–V) curves are recorded, attributed to a poor electrical contact between platinum and the oligothiophene moiety. However, a few devices offer well‐defined curves with a clear saturation, thus allowing an estimation of the mobility: 0.0035 cm² V^–1 s^–1 for quaterthiophene and 8 × 10^–4 cm² V^–1 s^–1 for terthiophene. In the first case, the on–off ratio reaches 1800 at a gate voltage of –2 V. Interestingly, the device operates at room temperature and very low bias, which may open the way to applications where low consumption is required.     

Selective Crystallization of Organic Semiconductors on Patterned Templates of Carbon Nanotubes

A method of patterning large arrays of organic single crystals is reported. Using single‐walled carbon nanotube (SWNT) bundles as patterned templates, several organic semiconductor materials were successfully patterned, including p‐type pentacene, tetracene, sexiphenylene, and sexithiophene, as well as n‐type tetracyanoquinodimethane (TCNQ). This study suggests that the selective growth of crystals onto patterned carbon nanotubes is most likely due to the coarse topography of the SWNT bundles. Moreover, we observed that the crystals nucleated from SWNT bundles and grew onto SWNT bundles in a conformal fashion. The dependence of the number of crystals on the quantity of SWNT bundles is also discussed. The crystal growth can be directly applied onto transistor source‐drain electrodes and arrays of organic single‐crystal field effect transistors are demonstrated. The results demonstrate the potential of utilizing carbon nanotubes as nucleation templates for patterning a broad range of organic materials for applications in optoelectronics.     

Organic thin-film field-effect transistors with MoO3/Al electrode and OTS/SiO2 bilayer gate insulator

An organic thin-film transistor (OTFTs) having OTS/SiO₂ bilayer gate insulator and MoO₃/Al electrode configuration between gate insulator and source–drain (S–D) electrodes has been investigated. Thermally grown SiO₂ layer is used as the OTFT gate dielectric and copper phthalocyanine (CuPc) for an active layer. We have found that using silane coupling agents, octadecyltrichlorosilane (OTS) on SiO₂, surface energy of SiO₂ gate dielectric is reduced; consequently, the device performance has been improved significantly. This OTS/SiO₂ bilayer gate insulator configuration increases the field-effect mobility, reduces the threshold voltage and improves the on/off ratios simultaneously. The device with MoO₃/Al electrode has similar source–drain current (I_DS) compared to the device with Au electrode at same gate voltage. Our results indicate that using double-layer of insulator and modified electrode is an effective way to improve OTFT performance.     

BST薄膜电容器的制备及其调谐性能研究

利用氩离子束溅射技术在SiO2/Si衬底上淀积Ba0.8Sr0.2TiO3(BST)薄膜,该薄膜在氧气气氛中500℃退火处理30 min,然后利用集成电路平面工艺将薄膜制作成叉指结构电容器。X-射线衍射仪(XRD)和扫描电镜(SEM)分析表明,BST薄膜具有钙钛矿结构,薄膜表面光滑,晶粒致密且分布均匀。调谐性能测试结果表明,该电容器具有较高的电容调谐率,在室温100 kHz频率下,对于2 V的直流偏压,其调谐率和损耗因子分别为62%和0.02。这说明具有此结构的BST薄膜电容器可望应用于微波集成电路。     

Ionic‐Liquid Gating of InAs Nanowire‐Based Field‐Effect Transistors

Here, the operation of a field‐effect transistor based on a single InAs nanowire gated by an ionic liquid is reported. Liquid gating yields very efficient carrier modulation with a transconductance value 30 times larger than standard back gating with the SiO₂/Si₊₊ substrate. Thanks to this wide modulation, the controlled evolution from semiconductor to metallic‐like behavior in the nanowire is shown. This work provides the first systematic study of ionic‐liquid gating in electronic devices based on individual III–V semiconductor nanowires: this architecture opens the way to a wide range of fundamental and applied studies from the phase transitions to bioelectronics.     

纳米级MOS器件中电子直接隧穿电流的研究

文章从分析量子力学效应对纳米级MOS器件的影响出发,采用顺序隧穿理论和巴丁传输哈密顿方法,建立了纳米级MOS器件直接隧穿栅电流的计算模型。通过和实验数据的比较,证明了该模型的有效性。计算结果表明,在纳米级MOS器件中,采用SiO2作栅介质时,1.5 nm厚度是按比例缩小的极限。该计算模型还可以用于高介电常数栅介质和多层栅介质MOS器件的直接隧穿电流的计算。     

Solution-grown aligned crystals of diketopyrrolopyrroles(DPP)-based small molecules:Rough surfaces and relatively low charge mobility

Field-effect transistors(FETs) of three diketopyrrolopyrroles(DPP)-based small molecules, 3,6-bis(5-phenylthiophene-2-yl)-2,5-bis(2-ethylhexyl)pyrrolopyrrole-1,4-dione(PDPPP), 3,6-bis(5-(4-fluorophenyl)thiophene-2-yl)-2,5-bis(2-ethylhexyl)pyrrolo pyrrole-1,4-dione(FPDPPPF) and 3,6-bis(5-(4-n-butylphenyl)thiophene-2-yl)-2,5-bis(2-ethylhexyl)pyrrolo pyrrole-1,4-dione(Bu PDPPPBu), have been studied in this work. Well aligned crystals of the three molecules were grown from para-xylene by droplet-pinned crystallization method. FETs based on these aligned crystals exhibit a hole mobility up to0.19 cm~2 V 1s 1and electron mobility up to 0.008 cm~2 V 1s 1. The achieved hole mobility is of the same order of magnitude as reported highest hole mobility for DPP-based small molecules, but it is much lower than that of the high-performance DPP-based polymers. The relative low mobility is mainly attributed to the rough crystal surfaces with steps and, thus, non-smooth charge transport channels at the interfaces between the crystals and the dielectrics. This work has implications for understanding the low charge mobility of DPP-based small molecules.