SSPA周边杂散光对响应度不均匀性的影响

根据实验现象，用半导体光电效应的基本原理，定性分析了自扫描光电二极管列阵周边杂散光对响应度不均匀性的影响，从装置和列阵结构上提出了相应的改进措施，有效地解决了列阵首尾部分二极管响应度的不均匀性。     

LP－MOCVD制作InGaAs／InPPIN光电二极管

采用ＬＰ－ＭＯＣＶＤ制作了ＩｎＧａＡｓ／ＩｎＰ平面型ＰＩＮ光电二极管。器件光敏面直径为７５μｍ，采用Ｚｎ扩散形成ＰＮ结，－６Ｖ偏置下其暗电流低达８～１３ｎＡ；反向击穿电压为６０Ｖ（１μＡ）。在没有增透膜时，对１．３μｍ注入光响应度为０．５６Ａ／Ｗ，光谱响应范围为０．９０～１．７０μｍ。     

New dark current component of InGaAs／InP HPDs confirmed by DLTS

The dark current of In_(0.47) Ga_(0.53) As/InP heterojunction photodiodes (HPDs) was analysed. We found that there exists a new dark current component-deep level-assisted tunnelling current.DLTS was used to measure the In_(0.47)Ga_(0.53)As/InP HPDs. An electronic trap which has a thermal activation energy of O.44 eV, level concentration of 3.10×10^(13)cm^(-3) and electronic capture cross section of 1.72×10^(12)cm^2 has been found.It s existence results in the new tunnelling current.     

Electrical and photoresponse characteristics of 8-(1H-indol-3-ylazo)-naphthalene-2-sulfonic acid/n-Si photodiode

In this paper, of primary interest is to synthesis 8-(1H-indol-3-ylazo)-naphthalene-2-sulfonic acid (INSA) and to evaluate the main parameters of Au/INSA/n-Si/Al diode in dark and under illumination. Different techniques are used for interpreting the proposed INSA chemical structure. The dark current-voltage measurements were achieved in the temperature range of 293?413 K. It is noticed that INSA films modify the interfacial barrier height of classical Au/n-Si junction. At low applied voltages, the I–V relation shows exponential behavior. The values ideality factor, n, and the barrier height, φ, are improved by heating. The abnormal trend of n and φ is discussed, and a homogenous barrier height of 1.45 eV is evaluated. The series resistance is also calculated using Norde's function and it changes inversely with temperature. The space charge limited current ruled with exponential trap distribution dominates at relatively high potentials, trap concentration and carriers mobility are extracted. The reverse current of the diode has illumination intensity dependence with a good photosensitivity indicating that the device is promising for photodiode applications.     

Hybrid ZnO-organic semiconductor interfaces in photodetectors: A comparison of two near-infrared donor-acceptor copolymers

Hybrid organic-inorganic photodiode interfaces have gained significant interest due to their unique physical properties such as mechanical flexibility and high photosensitivity. Two diketopyrrolopyrrole (DPP)-based donor-acceptor copolymers with different backbone conformations are characterized in an inverted non-fullerene photodiode architecture using ZnO nano-patterned films as the electron transport layer. The DPP copolymer with a thienothiophene unit (PBDT-TTDPP) is more planar and rigid compared to the DPP system with a thiophene unit connecting the donor and acceptor moieties within the monomer (PBDT-TDPP). The hybrid interfaces were optimized by using poly(3-hexylthiophene) (P3HT) as the p-type layer for monitoring the critical thickness and morphology of the ZnO layer. The maximum photoresponsivity from a P3HT:ZnO photodiode was found to be 56 mA/W. The photoresponsivity of PBDT-TTDPP:ZnO photodiodes were found to be more than two orders of magnitude higher than PBDT-TDPP:ZnO photodiodes, which is attributed to an enhanced transport of carriers due to the planar backbone conformation of the PBDT-TTDPP copolymer. Capacitance-voltage measurements from hybrid Schottky barrier interfaces further shed light into the nature of photocarriers and device parameters. First-principles time-dependent density-functional theoretical calculations yield a higher absorptivity for the PBDT-TTDPP dimer compared to PBDT-TDPP.     

二极管组高性能光电探测器阵列的设计

针对行波光电探测器阵列仅提高了光电探测器的输出功率而输出带宽未得到改善的特点,提出了一种由光电二极管组构成的高性能行波光电探测器阵列新结构.即把两个光电二极管级联后再将两个级联支路并联,然后在光电二极管组上串联电容构成单个阵列单元,再按照阵列式结构将这些阵列单元用电感连接起来构成新型行波光电探测器阵列.对比分析了行波光电探测器阵列新旧结构的功率合成、频率响应和回波损耗特性.在应用同等数量二极管的条件下,新型行波光电探测器阵列输出功率减少了一半,但工作带宽提高了一倍.此外,回波损耗随着阵列中应用二极管数目的增加相对于原阵列而言改善得更加明显.研究结果表明,本文提出的行波光电探测器阵列新结构能够在增加输出功率的同时提高工作带宽,更好地满足未来光载无线通信对光电探测器高功率宽带宽的需求.     

Design and testing of a self-powered 3D integrated SOI CMOS system

A self-powering 3D integrated circuit built using an SOI CMOS process is presented. The 3D integrated circuit has three tiers connected by vertical vias through the intertier oxides. The circuit elements are a photodiode array, a charge-integrating capacitor, and a local oscillator with an output buffer, each on a separate tier. The final system size is 250 μm × 250 μm × 696 μm. Our results demonstrate the circuit as a feasible proof-of-concept 3D “system”. The photodiode array stores charge on the capacitor and powers the oscillator as designed.     

New dark current component of InGaAs/InP HPDs confirmed by DLTS

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