基于锁相环电源噪声引起的周期抖动分析

针对电源噪声在时钟电路的锁相环中引起的抖动问题，通过分析周期抖动和相位抖动与电源噪声间的关系，提出了用于预测电源噪声引起的锁相环抖动峰峰值的计算公式。文中预测的抖动峰峰值与HSPICE的仿真结果间的误差最大为3%，说明了文中公式的有效性。     

Microstructure change in deuterium implanted CLAM steel induced by electron irradiation

As Reduced Activation Ferritic/Martensitic (RAFM) steel is considered the primary candidate for use as a structural material in fusion power reactors,many countries are developing different kinds of RAFM.China is developing new CLAM (China Low Activation Martensitic) steel.The study investigates microstructural changes in CLAM steel implanted with deuterium ions induced by 1250 keV electron irradiation from R.T.to 873 K,and observes both the growth and shrinkage of the defect clusters produced by deuterium ...     

Synchronization for IR‐UWB System Using a Switching Phase Detector‐Based Impulse Phase‐Locked Loop

Conventional synchronization algorithms for impulse radio require high‐speed sampling and a precise local clock. Here, a phase‐locked loop (PLL) scheme is introduced to acquire and track periodical impulses. The proposed impulse PLL (iPLL) is analyzed under an ideal Gaussian noise channel and multipath environment. The timing synchronization can be recovered directly from the locked frequency and phase. To make full use of the high harmonics of the received impulses efficiently in synchronization, the switching phase detector is applied in iPLL. It is capable of obtaining higher loop gain without a rise in timing errors. In different environments, simulations verify our analysis and show about one‐tenth of the root mean square errors of conventional impulse synchronizations. The developed iPLL prototype applied in a high‐speed ultra‐wideband transceiver shows its feasibility, low complexity, and high precision.     

一种改进的早迟积分型位定时同步方法

数字通信系统中,位定时同步是实现正常数字通信的必要条件.位定时同步方法有很多,其中早迟积分型位定时方法是应用最广泛的位定时方法之一.本文基于传统的早迟积分型位定时方法,通过改进早迟积分环的鉴相器,提出了一种改进的早迟积分型位定时方法.经Matlab仿真表明,在相同的环路滤波参数下,改进的早迟积分型位定时方法的环路收敛速度最优可以提高2倍.     

脉冲功率电容器用PbLa(ZrTi)O_3陶瓷性能研究

采用固相反应法制备了Pb0.96La0.06(Zr1-xTix)O3陶瓷,研究了Ti含量对所制陶瓷的电性能和储能特性的影响。结果表明,PbLa(ZrTi)O3陶瓷介电常数与电场强度呈非线性变化关系。当Ti含量x为0.08时,所测电滞回线细长狭窄,并呈下凹趋势,此时极化强度为22.18×10–6 C/cm2,储能密度为1.06 J/cm3。通过流延法制备的脉冲功率电容器击穿电压可大幅度提升,储能密度达1.95 J/cm3,具有高能量转换效率。     

一种针对压缩域信号的新型锁相环技术

针对通信信号压缩采样获得的压缩域信号频率、相位提取问题,提出了一种基于压缩感知的新型锁相环技术。通过深入研究压缩域的信号估计问题,提出了压缩域锁相环路,可以直接在压缩域同步跟踪信号频率和相位变化,不再需要高复杂度的信号重构处理。分析了环路模型及其估计性能,并针对该锁相环可行性和性能分别进行了仿真实验。仿真结果不仅验证了压缩域锁相环的可行性,同时表明该环路能够实现高动态信号的高精度频率提取。压缩域锁相环的应用潜力较大,例如可以作为压缩感知通信接收机的同步解调方法。     

基于导航系统的低功耗全集成频率综合器设计

针对双模卫星导航接收系统对集成度、功耗和面积的需求,研究了频率综合器的电路结构和频率规划,分析了频率综合器环路的参数设计,实现了片上集成环路滤波器,版图采用MIM和MOS电容堆叠的方式节省了面积,电容电阻采用了加权的方式,使环路带宽可调.采用高速TSPC结构的D触发器构成双模预分频器,降低了整体电路的功耗.利用基于0.18 μmRF CMOS工艺实现了低功耗全集成的频率综合器,芯片面积0.88 mm2,功耗18.5 mW,相位噪声-94 dBc/Hz@100 kHz,杂散-68 dBc.测试结果证明了该电路系统参数设计和结构改进是合理和有效的,各参数性能满足系统要求.     

All-digital controlled boost DC–DC converter with all-digital DLL-based calibration

Traditional digital controls mostly use digital–analog converters to convert input and output voltages into digital coding to achieve control. This paper proposes the use of two digital ramps with two different frequencies to replace a digital–analog converter. This approach can produce seven bit resolution for the DPMW signal. In addition, we use an all-digital DLL phase correction concept to further enhance the resolution of the DPWM signal by an additional three bits, resulting in 10-bit DPWM signal resolution. The proposed circuit uses 0.35 μm CMOS processes, with a core area of 0.987 mm², a system switching frequency of 500 KHz, an input voltage range of 3.3–4.2 V, and an output voltage range of 5 V. Output voltage measurement accuracy reaches 99%, while the system reaches efficiency of 91% with output loads of up to 500 mA.     

基于波长敏感的耦合器动态增益平坦L波段EDFA理论与实验

掺铒光纤放大器(EDFA)的增益平坦化是波分复用(WDM)系统的重要问题,文章通过理论和实验提出一种新型的增益平坦滤波器,即一种耦合比随波长变化的耦合器与偏振控制器(PC)构成光纤环形镜,调节光纤环形镜内的PC的状态,从而改变光纤环形镜的反射谱线的位置和深度,使其匹配EDFA的增益谱,实现对L波段EDFA增益平坦,实验结论得出,平坦后的光谱在1562nm~1605nm带宽内增益平坦度为±0.7d B。