铁路建设工程安全管理信息系统的设计与实现方法

借助信息化技术加强对铁路建设项目的安全管理,成为当前在新形势下提高铁路建设效率,保障工程质量的有效途径。本文提出了基于Web-GIS技术,通过数据集成,构建铁路建设工程安全管理系统,并对系统的功能与架构进行了阐述。     

倍频傅里叶域模式锁定扫频激光源

搭建完成了基于单偏振助推光学放大器的傅里叶域模式锁定扫频激光源,并在此基础上实现了倍频傅里叶域模式锁定扫频激光源,将光源的成像速度提高了一倍。该倍频激光源输出功率达到2mW左右,扫描频率为45kHz,输出光谱的中心波长为1 315nm,光谱宽度为107nm。利用该光源进行相干层析成像实验时,系统的A-Scan速率为90kHz,纵向分辨率为12.9μm左右,相干长度为0.9mm左右,灵敏度为105dB。     

Design of self-bias tail transistor technique for low phase noise CMOS VCO with harmonic suppression using capacitance ground

This paper presents a low phase noise wideband CMOS VCO based on the self-bias tail transistor technique and harmonic suppression using a capacitance ground. This VCO utilizes switching capacitor arrays in which four channels are able to be selected for multi-band application. Moreover, the design of CMOS VCO makes good use of the self-bias tail transistor and capacitance ground filter technique to reduce the phase noise. The MOS varactors are used as fine tuning for wideband operating application. The fully integrated VCO provides excellent performance with high FOM −193 dBc/Hz. The bandwidth of the frequency is 1.1 GHz and the tuning range is 13.8%. The power dissipation of the core circuit is 8.28 mW under a 1.8 V supply and phase noise is measured as low as −123.6 dBc/Hz at 1 MHz offset under 8.5 GHz oscillation frequencies. This VCO was made by the TSMC 0.18 μm 1P6M CMOS standard process and the chip area is 0.75×0.69 (mm²).     

A process-tolerant out-of-band blocker rejection technique for SAW-less receivers

In this paper, an active filtering technique is presented which is capable of filtering the out-of-band blockers in wireless receivers. The concept is based on the feedforward cancellation technique where a blocker replica is subtracted at the output of the low-noise amplifier (LNA). In contrast to the previously reported feedforward cancellation methods, exact gain and phase matching are easily obtained in the proposed architecture to produce a highly selective narrowband frequency response at the output of the LNA with wide rejection bandwidth. For the proof of concept, the system is implemented in a 65 nm CMOS technology. It occupies a total area of 0.8 mm² and the current consumption is 24 mA from a 1.2 V supply. The system post-layout simulations showed a blocker rejection of more than 33 dB for blocker signals 100 MHz away from the desired signal when the feedforward path is activated. The noise figure (NF) of the entire system is 3.8 dB that degrades to 5.8 dB when the feedforward path is activated.     

Frequency presetting and phase error detection technique for fast-locking phase-locked loop

A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35 μm CMOS process, with a supply voltage of 3.3 V.     

Effect of Ag photo-doping on structural,optical and phase change properties of GeTe chalcogenide films

This paper reports the effect of Ag photo-doping on optical, electrical and structural properties of GeTe:Ag thin films. The absence of sharp diffraction peak confirms the amorphous nature of as-deposited and photo-doped films. The decrease in reflectance of GeTe:Ag bilayer films with photo-doping reaction time has been observed. The RAMAN spectrum showed the characteristic Raman bands for GeTe₄ (127 cm⁻¹), long chain interactions of Te–Te chains (145 cm⁻¹) and a broad peak for Ge–Ge vibrations (275 cm⁻¹) without appreciable change in their position/shape with photodoped Ag concentration. The electrical resistivity measurement shows that photo-doping of Ag led to sharp amorphous-crystalline phase transition along with an increase in transition temperature and resistivity value in both amorphous as well as crystalline state. The annealing of photo-doped GeTe:Ag samples showed an enhancement in the crystallinity of GeTe phase without any segregation of Ag phases in annealed samples. The preferential formation of GeTe (200) phase upon crystallization has been observed for GeTe:Ag films. Different optical parameters have been calculated for photo-doped and annealed samples and are discussed in conjunction with the modification of network structure of GeTe with inclusion of photo-doped Ag content.     

频差对方向图综合的影响及解决方法

为解决各调频发射机开机时载波频差对天线阵列方向图综合的影响,这里利用了DFT最大值谱线及与其相邻两根谱线系数的实部（或虚部）进行插值得到各个发射机载波频率的估算值,然后提出了一种有效的补偿方法,以减少频差引起的瞬时相位差对方向图综合的影响。仿真实验表明：此方法频率估算精度较高,采用该方法可以有效的解决频差对天线阵列方向图综合的影响。     

一种基于“相位距离”降低CPM解调复杂度的新算法

连续相位调制(CPM)是一种恒包络的高效调制方式,由于其解调算法复杂度高,其应用长期以来受到限制。传统的CPM解调算法基本上是基于幅度信息而未考虑相位信息,因此复杂度较高。本文提出了一种依据CPM信号特征的相位距离的定义,利用2RC-4CPM对该定义的有效性进行了验证,并将其应用于降低最大似然序列检测算法的路径数,从而大幅降低了最优接收机解调的复杂度。仿真表明,在选取适当门限值的情况下,基于相位距离的最大似然序列检测算法性能接近最优接收机。     

基于HFSS设计同轴腔调谐滤波器

同轴腔调谐滤波器在军事通信设备中具有广泛应用.论述了该类滤波器的设计原理,详细分析了腔间耦合孔和输入、输出耦合环的位置和大小的设计,在此基础上应用高频结构仿真软件(HFSS),对L波段调谐滤波器的实例进行仿真设计.结果表明仿真拟合准确,说明应用HFSS仿真软件能够很好的描述调谐滤波器的关键设计内容.     

FPGA芯片内数字时钟管理器的设计与实现

在FPGA芯片内,数字时钟管理器(DCM)不可或缺,DCM主要完成去时钟偏移、频率综合和相位调整的功能,其分别由延迟锁相环(DLL)、数字频率合成器(DFS)以及数字相移器(DPS)三个模块来实现。对这三个模块的原理及设计进行了详细地阐述,并给出了仿真结果,该DCM电路通过了0.13μm工艺流片。测试结果表明,在低频模式下,该DCM能工作在24～230 MHz之间;在高频模式下,该DCM能工作在48～450 MHz之间,其输入及输出抖动容忍度在低频模式下能达到300 ps,在高频模式下能达到150 ps。