基于SST89C54/58的单片机仿真器的设计

介绍美国SST公司的51系列单片机SsT89C54／58的程序存储器的结构特点以及基于SST89C54／58的KEILC51单片机仿真器的设计。     

新标准H.264的核心技术与应用前景

围绕视频传输要求高效、可靠和网络友好的三个焦点问题,深入研究H.264标准编码层压缩性能的提升、网络适配层的无缝集成和编/解码器的容错性能;以基于包交换的IP视频信息包为例,重点分析H.264对因特网RTP/UDP/IP协议的映射过程;阐述H.264在视频移动通信、视频流服务、数字电视广播与存储领域的典型应用特点;指出H.264对视频源压缩、信道有效利用、缓解视频传输瓶颈的影响和发展前景.     

微波MCM电路的设计与制作

本文介绍一种新的封装技术－微波多芯片组件（ＭＣＭ）技术。详细阐述了其设计环节并分析了设计要点，提出了通用的设计方法。此外还介绍了微波ＭＣＭ电路的制作流程。     

Sequential design for achieving estimated accuracy of global sensitivities

Global sensitivity analysis provides information on the relative importance of the input variables for simulator functions used in computer experiments. It is more conclusive than screening methods for determining if a variable is influential, especially if a variable's influence is derived from its interactions with other variables. In this paper, we develop a method for providing global sensitivities with estimated accuracy. A treed Gaussian process serves as a statistical emulator of the black box function. A sequential experimental design makes effective and efficient use of simulator evaluations by adaptively sampling points that are expected to provide the maximum improvement to the emulator model. The method accounts for both sampling error and emulator error. Copyright © 2014 John Wiley & Sons, Ltd.     

Fast convolution based thermal model for 3D-ICs: Methodology,accuracy analysis and package impact

Thermal analysis is essential in 3D-IC technology due to the reduced footprint and higher power densities compared to conventional 2D packaging. Computationally fast thermal models (FTMs) are being developed for fast evaluation of the temperature distribution in 3D packages. The steady state FTM discussed in this paper is based on Green׳s function theory and exploits convolution and the fast Fourier transform to compute the temperature profiles starting from matrices storing the power dissipation densities (power maps) and the temperature responses to hot spots. However, this methodology is not directly applicable for finite dimensional structures. The method of images is exploited to include the effect of insulating lateral boundary conditions. The number of images needed to ensure accurate results depends on the specific structure of the stack. A fast method to compute it is proposed together with a short analysis of its dependence on some system parameters. A two dies stack case study is thermally analyzed showing good agreement with the finite element method (FEM) results (errors less than 0.5%). The computational time is also discussed indicating a $O(N\log N)$ behavior, where N is the number of elements in the extended power maps, which include images, as well as a 70 times speed up with respect to FEM. Finally, since in the FTM the package is implicitly included in the boundary conditions, the thermal impact of its real configuration is investigated.     

Chip-Package Interaction in 3D stacked IC packages using Finite Element Modelling

Chip Package Interaction (CPI) gained a lot of importance in the last years. The reason is twofold. First, advanced node IC technologies requires dielectrics in the BEOL (back-end-of-line) with a decreasing value for the dielectric constant k. These so-called (ultra) low-k materials have a reduced stiffness and reduced adhesion strength to the barrier materials, making the BEOL much more vulnerable to externally applied mechanical stress due to packaging. Secondly, advanced packaging technologies such as 3D stacked IC’s use thinned dies (down to 25 μm) which can cause much higher stresses at transistor level, resulting in electron mobility shifts of the transistors. Also the copper TSV (through-silicon-via) generates local stress which affects the device performance. This paper considers both the packaging impact on BEOL integrity and transistor mobility shifts for 3D stacked IC (integrated circuit) technologies.     

Compact thermal modeling for packaged microprocessor design with practical power maps

In this paper, we propose a new behavioral thermal modeling technique for high-performance microprocessors at package level. Firstly, the new approach applies the subspace identification method with the consideration of practical power maps with correlated power signals. We show that the input power signal needs to meet an independence requirement to ensure the model predictability and propose an iterative process to build the models with given error bounds. Secondly, we show that thermal systems fundamentally are nonlinear and then propose a piecewise linear (PWL) scheme to deal with nonlinear effects. The experimental results validated the proposed method on a realistic packaged integrated system modeled by the multi-domain/physics commercial tool, COMSOL. The new piecewise linear models can model thermal behaviors over wide temperature ranges or over different thermal boundary convective conditions due to different fan speeds. Further, the PWL modeling technique can lead to much smaller model order without accuracy loss, which translates to significant savings in both the simulation time and the time required to identify the reduced models compared to the simple modeling method by using the high order models.     

基于DDS的动态多普勒模拟器的设计与应用

在航天测控领域中,测控系统的动态捕获、跟踪性能和测量精度是非常重要的因素,为检测测控雷达的动态捕获、跟踪性能和测量精度,对直接数字频率合成技术进行了分析,提出基于DDS的动态多普勒模拟器的设计方案,产生70MHz为中心的高精度准确度的频率,达到对测控雷达中频单元动态测试的目的,此设计在工程中的应用效果良好。     

IC封装中引线键合互连特性分析

研究了芯片封装中键合线的建模和模型参数提取方法.根据二端口网络参量,提出了单键合线的П型等效电路并提取了模型中的R、L和C参量.最后,设计出一个简单、低成本的测试结构验证了仿真分析结果.     

高密度封装技术推动测试技术发展

本文主要介绍了几种新型测试技术的特点,并对未来测试技术的发展趋势及方向进行了初步分析.