非晶化注入技术在NiSi SALICIDE工艺中的应用

在pn结形成之后借助非晶化Si离子注入技术可以将结表面Si单晶层非晶化. 作者研究了这种非晶化处理对Ni硅化反应的影响. 实验发现，非晶化处理可以促进Ni在低温下与衬底Si的反应，而且在低温下Ni/Si可以直接反应形成NiSi. 实验结果表明这种非晶化未对硅化反应过程中杂质的再分布产生影响，但是剖面透射电镜分析表明，这种非晶化所需能量需要合理优化.     

Nickel silicide as a contact material for submicron CMOS devices

Nickel monosilicide (NiSi) is an attractive alternative to the currently used silicides for the coming generations of deep submicron complementary metaloxide-semiconductor (CMOS) devices. This silicide material has a resistivity, which is comparable to that of TiSi₂ or CoSi₂, but consumes less silicon for its formation. The silicide silicon interface is relatively planar and, unlike TiSi₂, its resistivity does not change with the linewidth for narrow lines. However, the thermal stability of NiSi is relatively poor at the currently used temperatures during process integration. Recent studies have shown that the stability of these films could be increased substantially through the small addition of alloy elements, which do not increase the resistivity of the NiSi film. Morever, it has been demonstrated that the addition of a small amount of alloy elements significantly reduces diode leakage, possibly due to the suppression of silicide spike formation as a result of alloy addition. This paper will present and discuss the details of these experimental results.     

NiSi contact metallization using electroless Ni deposition on Pd-activated self-assembled monolayer (SAM) on p-type Si(1 0 0)

In this paper we describe a method to form NiSi contacts using electroless plating of Nickel or Ni alloy on Pd activated self-assembled monolayer (SAM) on p-type Si(1 0 0). Such method allows uniform deposition of very thin, <30 nm, Ni or Ni alloy films. Clean, oxide free, Si substrate was covered with aminopropyltriethoxysilane (APTES) self-assembled monolayer. The surface was activated with Pd-citrate solution followed by electroless plating. The samples were annealed for 1 h in vacuum (∼10⁻⁶ Torr) forming the silicide layer. The annealing temperatures were 400 °C for NiP alloy and 500 °C for NiPW alloy. X-ray diffraction (XRD) measurement confirmed the presence of NiSi phase after annealing. The silicides material properties were characterized using secondary electron microscopy (SEM) analysis, X-ray diffraction (XRD) and X-ray photon spectroscopy (XPS) profiling. The results are reported and summarized.     

Kleppa type calorimeter for the study of high temperature processes

A Kleppa type microcalorimeter was designed and constructed for the application to measure the thermal change in a reaction tube at T>1300 K. The details of new calorimeter are described. In order to verify the performance of the new calorimeter, the standard enthalpies of formation for NiSi and Ni₃Al were measured by direct synthesis in the calorimeter at T=1323 K. The enthalpies of formation obtained were −(79.3 ± 1.8) and −(189.3 ± 6.3) kJ · mol⁻¹ for NiSi and Ni₃Al, respectively. A comparison of results in the present work with available reported values has been made.     

锗预非晶化注入对镍硅(NiSi)金属栅功函数的影响研究

随着超大规模集成电路技术的发展,CMOS器件的制备过程需要同时引入金属栅和超浅结等新的先进工艺技术,因此各种新工艺的兼容性研究具有重要意义.本文研究了超浅结工艺中使用的锗预非晶化对镍硅(NiSi)金属栅功函数的影响.对具有不同剂量Ge注入的NiSi金属栅MOS电容样品的研究表明,锗预非晶化采用的Ge注入对NiSi金属栅的功函数影响很小(小于0.03eV),而且Ge注入也不会导致氧化层中固定电荷以及氧化层和硅衬底之间界面态的增加.这些结果表明,在自对准的先进CMOS工艺中,NiSi金属栅工艺和锗预非晶化超浅结工艺可以互相兼容.     

Schottky barrier height of a new ohmic contact NiSi2 to n-type 6H-SiC

We present a new ohmic contact material NiSi₂ to n-type 6H-SiC with a low specific contact resistance. NiSi₂ films are prepared by annealing the Ni and Si films separately deposited on (0 0 0 1)-oriented 6H-SiC substrates with carrier concentrations (n) ranging from 5.8×10¹⁶ to 2.5×10¹⁹ cm⁻³. The deposited films are annealed at 900 °C for 10 min in a flow of Ar gas containing 5 vol.% H₂ gas. The specific contact resistance of NiSi₂ contact exponentially decreases with increasing carrier concentrations of substrates. NiSi₂ contacts formed on the substrates with n=2.5×10¹⁹ cm⁻³ show a relatively low specific contact resistance with 3.6×10⁻⁶ Ω cm². Schottky barrier height of NiSi₂ to n-type 6H-SiC is estimated to be 0.40±0.02 eV using a theoretical relationship for the carrier concentration dependence of the specific contact resistance.     

Effect of a thin W, Pt, Mo, and Zr interlayer on the thermal stability and electrical characteristics of NiSi

It is reported that the thermal stability of NiSi is improved by employing respectively the addition of a thin interlayer metal (W, Pt, Mo, Zr) within the nickel film. The results show that after rapid thermal annealing (RTA) at temperatures ranging from 650 °C to 800 °C, the sheet resistance of formed ternary silicide Ni(M)Si was less than 3 Ω/□, and its value is also lower than that of pure nickel monosilicide. X-ray diffraction (XRD) and raman spectra results both reveal that only the Ni(M)Si phase exists in these samples, but the high resistance NiSi₂ phase does not. Fabricated Ni(M)Si/Si Schottky barrier devices displayed good I-V electrical characteristics, with the barrier height being located generally between 0.65 eV and 0.71 eV, and the reverse breakdown voltage exceeding to 40 V. It shows that four kinds of Ni(M)Si film can be considered as the satisfactory local connection and contact material.     

深槽Ni(Pt)Si/Si肖特基二极管特性研究

采用15nmNi/1.5nmPt/15nmNi/Si结构在600～850°C范围内经RTP退火的方法形成Ni(Pt)Si薄膜,其薄膜电阻低且均匀一致。比形成较低电阻率的NiSi薄膜的温度提高了150°C。在850°CRTP退火后形成的Ni(Pt)Si/Si肖特基势垒二极管I-V特性很好,其势垒高度ΦB为0.71eV,改善了肖特基二极管的稳定性。实验表明在肖特基二极管中引入深槽结构,可以大幅度地提高其反向击穿电压。在外延层浓度为5E15cm-3时,深槽器件的击穿电压可以达到80V,比保护环器件高约30V。     

用金属诱导-准分子激光晶化法制备多晶硅薄膜

提出了一种新的晶化方法——金属诱导-准分子激光晶化法(MI-ELA)。该方法在制备多晶硅(p-Si)薄膜中包括两个步骤：第一步是用镍金属诱导方法(MIC)通过热退火形成NiSi2；第二步是再通过准分子激光退火方法(ELA)晶化形成p-Si。通过用XRD、Raman与SEM测试，研究了p-Si的结晶性和表面形貌特征。研究发现，MI-ELA方法制备的p-Si与传统的ELA方法和MIC方法相比在形貌上不一样，而且从XRD的特征峰强度可以看出在结晶度上有进一步提高。这个结果源于用MIC方法形成的且与e-Si晶格匹配的NiSi2在ELA中起到晶核的作用。这种晶化方法说明，在ELA中，晶粒生长不再仅仅依赖于熔融非晶硅和氧化物表面上残存的随机的固体a-Si作为成核媒介。这种方法不但可以提供晶粒稳定生长条件，而且也可能使获得更大晶粒粒度的激光晶化能量展宽。     

Ni- and Co-based silicides for advanced CMOS applications

The scaling behavior of Co, Co–Ni and Ni silicides to sub-40 nm gate length CMOS technologies with sub-100 nm junction depths was evaluated. Limitations were found for Co and Co–Ni alloy silicides, which exhibited an increase in sheet resistance at gate lengths below 40 nm and required high processing temperatures to achieve low junction leakage. Ni silicide was shown, in contrast, to have good scaling behavior, with a decrease in sheet resistance for decreasing gate lengths down to 30 nm, lower diode leakage (at similar sheet resistance) and lower silicide to p+ Si contact resistance than Co silicide. Key material issues impacting the applicability of NiSi to CMOS technologies were investigated. Studies of the kinetics of Ni₂Si growth were used to design a process that avoids excessive silicidation of small features. The thermal degradation mechanisms of NiSi films were also studied. Thin films degraded morphologically with activation energies of 2.4 eV. Thick films degraded morphologically at low temperatures and by transformation to NiSi₂ at high temperatures, suggesting a higher activation energy for the latter mechanism. Pt alloying was shown to help stabilize NiSi films against morphological degradation.