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基于MATLAB语言的自动控制原理多媒体教学研究 总被引:1,自引:1,他引:0
结合我校自动化专业教学,从培养高素质,复合型人才的角度,在教学中引入目前世界上流行的MATLAB软件,并把MATLAB语言应用于经典控制系统设计和分析中,在自动控制原理多媒体辅助教学方面做了一些有益尝试和探索,取得了满意的教学效果。 相似文献
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CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing 总被引:2,自引:0,他引:2
As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features.This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundray Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation.These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A tool-box environment is provided, in order to automatically generate the needed component to build the chosen SoC test architecture. 相似文献
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In asynchronous transfer mode (ATM) networks, fixed length cells of 53 bytes are transmitted. A cell may be discarded during transmission due to buffer overflow or a detection of errors. Cell discarding seriously degrades transmission quality. The quality degradation can be reduced by employing efficient forward error control (FEC) to recover discarded cells. In this paper, we present the design and implementation of decoding equipment for FEC in ATM networks based on a single parity check (SPC) product code using very‐large‐scale integration (VLSI) technology. FEC allows the destination to reconstruct missing data cells by using redundant parity cells that the source adds to each block of data cells. The functionality of the design has been tested using the Model Sim 5.7cXE Simulation Package. The design has been implemented for a 5 ° 5 matrix of data cells in a Virtex‐E XCV 3200E FG1156 device. The simulation and synthesis results show that the decoding function can be completed in 81 clock cycles with an optimum clock of 56.8 MHz. A test bench was written to study the performance of the decoder, and the results are presented. 相似文献
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In this paper, the special construction of a parallel robot, called spatial servopneumatic multi-axis test facility, will be discussed. The investigations include the following aspects: (i) the laboratory set-up of the robot, (ii) various results obtained in laboratory experiments, taking into account quite different control algorithms and command-input signals, (iii) a comparison of the laboratory experiments with the computer simulations of Part I of this paper, and ({vi}) a quality check of the results compared with the cost of the different controller realizations. The results of both the computer simulations and the laboratory experiments show: (i) The dynamic behavior of the parallel structure can be tremendously improved by using sophisticated nonlinear control algorithms. (ii) This improvement has to be paid by a drastically increased amount of work for deriving the model equations and control algorithms, and by augmented hardware cost of the sensing elements and controller electronics. (iii) Carefully developed model equations and identified model parameters provide theoretical models of the complex parallel structure that are very close to reality. This enables the design engineer to systematically investigate constructive alternatives of the design parameters, sensor and actuator concepts, and control strategies of the MAP prior to their hardware realization.This work has been supported by the German Science Foundation (DFG) under Contract No. Ha 1666/6-3. 相似文献
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LB11820M是日本SANYO(三洋)公司开发的三相直流无刷电机驱动芯片。它具备开环三相电机控制所需的全部有效功能,并且具有比较完善的保护电路。文中介绍了LB11820M的特点、功能和工作原理,给出了其典型应用电路。 相似文献
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We consider the optimal service control of a multiclass M/G/1 queueing system in which customers are served nonpreemptively and the system cost rate is additive across classes and increasing convex in the numbers present in each class. Following Whittle's approach to a class of restless bandit problems, we develop a Langrangian relaxation of the service control problem which serves to motivate the development of a class of index heuristics. The index for a particular customer class is characterised as a fair charge for service of that class. The paper develops these indices and reports an extensive numerical investigation which exhibits strong performance of the index heuristics for both discounted and average costs. 相似文献