一种数模混合电路状态的波形分析方法

本文针对数模混合电路仿真波形的特点,提出一种以开关事件为基础的状态序列数据结构,有效地压缩存储空间;同时,基于这种数据结构,本文还提出一种仿真波形比较方法,该方法根据仿真波形自动检测划分电路的状态,并能在考虑一定容限范围的前提下实现波形比较,有效地提高了模拟信号以及数字信号完整性的验证效率.这种方法已成功运用到本文开发的数模混合时移波形比较软件系统中,并已在Intel技术开发(上海)公司内部推广使用.     

Analog-CMDA based interfaces for MEMS gyroscopes

This work moves toward the state-of-the-art for the interfaces usually employed for three-axes micromachined gyroscopes. Several architectures based on multiplexing schemes in order to extremely simplify the analog front-end which can be based on a single charge amplifier are analyzed and compared. This paper presents a novel solution that experiments an innovative readout technique based on a special analog-CDMA (Code Division Multiplexing Access); this architecture can reach a considerable reduction of the analog front-end with reference to other multiplexing schemes. Many family codes have been considered in order to find the best trade-off between performance and complexity. System-level simulations prove the effectiveness of this technique in processing all the required signals. Finally, a case study is analyzed: a comparison with the SD740 micro-machined integrated inertial module with a tri-axial gyroscope by SensorDynamics AG is provided.     

基于数模混合仿真的PLL系统设计

介绍了数模混合信号仿真的设计流程，说明了一种在混合设计的各个层次上对系统进行仿真验证的自上而下的设计方法。在PLL（Phase-Locked Loop）系统设计中，给出了VCO的数学模型和Verilog-A行为级模型．实现了系统行为级模型和晶体管级电路的设计和仿真，并对结果进行了比较。这种设计方法已应用于一种电荷泵锁相环电路设计中，验证了这种设计方法的可行性和有效性。     

集成电路测试相关标准研究与探讨

重点研究了纯数字信号、混合信号和片上系统测试的一些问题及相关标准，阐述了各标准的作用，分析了这些标准在实际应用中存在的一些问题及其局限性。     

Test of switched-capacitor ladder filters using OBT

In this paper, a way to test switched-capacitors ladder filters by means of Oscillation-Based Test (OBT) methodology is proposed. Third-order low-pass Butterworth and Elliptic filters are considered in order to prove the feasibility of the proposed approach. A topology with a non-linear element in an additional feedback loop is employed for converting the Circuit Under Test (CUT) into an oscillator. The idea is inspired in some author's previous works (G. Huertas, D. Vázquez, A. Rueda, J.L. Huertas, Oscillation-based Test Experiments in Filters: a DTMF example, in: Proceedings of the International Mixed-Signal Testing Workshop (IMSTW'99), British Columbia, Canada, 1999, pp. 249–254; G. Huertas, D. Vazquez, E. Peralías, A. Rueda, J.L. Huertas, Oscillation-based test in oversampling A/D converters, Microelectronic Journal 33(10) (2002) 799–806; G. Huertas, D. Vázquez, E. Peralías, A. Rueda. J.L. Huertas, Oscillation-based test in bandpass oversampled A/D converters, in: Proceedings of the International Mixed-Signal Test Workshop, June 2002, Montreaux (Switzerland), pp. 39–48; G. Huertas, D. Vázquez, A. Rueda, J.L. Huertas, Practical oscillation-based test of integrated filters, IEEE Design and Test of Computers 19(6) (2002) 64–72; G. Huertas, D. Vázquez, E. Peralías, A. Rueda, J.L. Huertas, Testing mixed-signal cores: practical oscillation-based test in an analog macrocell, IEEE Design and Test of Computers 19(6) (2002) 73–82). Two methods are used, the describing function approach for the treatment of the non linearity and the root-locus method for analysing the circuit and predicting the oscillation frequency and the oscillation amplitude. In order to establish the accuracy of these predictions, the oscillators have been implemented in SWITCAP (K. Suyama, S.C. Fang, Users' Manual for SWITCAP2 Version 1.1, Columbia University, New York, 1992). Results of a catastrophic fault injection in switches and capacitors of the filter structure are reported. A specification-driven fault list for capacitors is also defined based on the sensitivity analysis. The ability of OBT for detecting this kind of faults is presented.     

A high-performance VHDL-based virtual tester: a concept and a solution

Virtual test (VT) is a powerful technique to cut the time-to-market especially for SoC products. VT allows debugging mixed-signal test programs in a simulation environment if a fast and sufficiently accurate chip model can be made available several weeks before first silicon. VHDL behavioural models were found to cover both the needs of designers for sign-off simulation on chip level and of test engineers for VT. This paper presents a high-performance VT solution based on pure VHDL modelling of the hardware involved, a VHDL-based virtual tester concept and a snapshot test data extractor linking the test program to a simulator.