A threshold voltage model MOSFETs considering for high-k gate-dielectric fringing-field effect

In this paper, a threshold voltage model for high-k gate-dielectric metal-oxide-semiconductor field-effect transistors （MOSFETs） is developed, with more accurate boundary conditions of the gate dielectric derived through a conformal mapping transformation method to consider the fringing-field effects including the influences of high-k gate-dielectric and sidewall spacer. Comparing with similar models, the proposed model can be applied to general situations where the gate dielectric and sidewall spacer can have different dielectric constants. The influences of sidewall spacer and high-k gate dielectric on fringing field distribution of the gate dielectric and thus threshold voltage behaviours of a MOSFET are discussed in detail.     

真空开关CuCrTe触头材料的组织与性能

为了改进混粉烧结CuCrTe触头材料的缺陷并且增大触头材料的开断能力,采用真空熔铸法制造工艺研制了CuCrTe触头材料并对其性能进行了测试。结果表明,真空熔铸CuCrTe材料在显微组织、抗熔焊性能、开断电流能力、截流水平、耐电压水平方面都优于粉末冶金CuCr50材料,特别是开断电流能力提高了26%多,是一种有发展前途、性能优良的触头材料。     

自由空间与偏振无关的1×N和N×1光开关设计

基于光开关在全光通信和光互连网络中的重要作用，设计了由偏振光分束器（PBS）、相位型空间光调制器（PSLM）和反射镜构成的1×N和N×1光开关模块，其中N＝2m，m＝1，2，3…。该设计利用PSLM对信号光偏振态的控制，在自由空间实现信号的路由和切换，信号光的P光分量和S光分量同时参与工作，并在输出端口重新会合，因此光开关表现出与信号光偏振态无关的特点。同时，该光开关所用器件少，具有结构简单紧凑、控制方便灵活和操作迅速快捷等特点，而且具有很强的重构与升级能力，对于构建大规模的交换矩阵具有一定的作用。     

一种高速高精度采样/保持电路

介绍了一种用于12bit,100MS/s流水线模数转换器前端的采样/保持电路的设计.该电路在3V电源电压100MHz采样频率时,输入直到奈奎斯特频率仍能够达到108dB的无杂散动态范围(SFDR)和77dB的信躁比(SNR).论文建立了考虑开关之后的采样保持电路的分析模型,并详细研究了电路中开关组合对电路性能的影响,同时发现了传统的栅源自举开关(bootstrapped switch)中存在的漏电现象并对其进行了改进,极大地减小了漏电并提高了电路的线性性能.     

惯性冲击对低真空封装的RF MEMS电容开关性能的影响

分析了外界惯性冲击对低真空封装的旁路电容式RF MEMS开关性能的影响.得到了近似计算外界惯性冲击引起位移的解析式.在已知最大容许插入损耗和外部惯性冲击环境条件下,MEMS开关支撑梁的最小机械刚度常数以及外部惯性冲击引起的插入损耗可以根据该式得到.通过RF MEMS电容式开关实例,表明设计低真空封装的RF MEMS电容式开关时应考虑外部环境因素.可见,RF MEMS开关用低真空封装可以减小空气阻尼、改善开关速度和执行电压的同时,开关的性能却容易受外界环境因素的影响.该研究对低真空封装的RF MEMS电容式开关的优化设计很有意义.     

硅基光子材料和器件的进展

评述硅基光子材料和器件的进展,包括硅二极管的受激发射、具有量子结构的RCE(谐振腔增进型)光电二极管、MOS高频光调制器、SOI光开关阵列和可调谐波长滤波器,重点介绍低插入损耗、快响应的SOI基热光波导开关阵列的最新结果.以SOI为基片,成功地研制出带有全内反射(TIR)镜的重排无阻塞型光开关阵列,并首次研制出16×16阻塞型光开关阵列.在1.55μm波段,插入损耗和偏振相关性随着器件长度的增加而略微增大.如果器件的末端镀上抗反射膜,插入损耗会降低2～3dB,这些器件的上升和下降时间分别为2.1和2.3μs.     

High-voltage LDMOS transistors fully compatible with a deep-submicron 0.35 μm CMOS process

This work presents the design of LDMOS transistors fully compatible with a standard CMOS process, only requiring mask layout manipulation. A conventional 0.35 μm CMOS process was elected to demonstrate the viability of the approach. The prototyped LDMOS transistor exhibits a breakdown voltage of 24 V, which represents an improvement of 31% when compared with the high-voltage extended-drain NMOS available in the process library, while other static parameters remain in the same range. Furthermore, this solution enables the CMOS integration of a high-voltage pass-transistor, as a consequence of the formation of an isolated lightly doped p-type region inside the n-well.     

An analytical drain current model for graded channel cylindrical/surrounding gate MOSFET

In the present paper, a comprehensive drain current model incorporating various effects such as drain-induced barrier lowering (DIBL), channel length modulation and impact ionization has been developed for graded channel cylindrical/surrounding gate MOSFET (GC CGT/SGT) and the expressions for transconductance and drain conductance have been obtained. It is shown that GC design leads to drain current enhancement, reduced output conductance and improved breakdown voltage. The effectiveness of GC design was examined by comparing uniformly doped (UD) devices with GC devices of various L₁/L₂ ratios and doping concentrations and it was found that GC devices offer superior characteristics as compared to the UD devices. The results so obtained have been compared with those obtained from 3D device simulator ATLAS and are found to be in good agreement.     

Effects of background doping concentration on electrostatic discharge protection of high voltage operating extended drain N-type MOS device

In this study, the effects of background doping concentration (BDC) of a high voltage operating extended drain N-type MOSFET (EDNMOS) device on electrostatic discharge (ESD) protection performances were evaluated. The EDNMOS device with low BDC suffers from strong snapback in the high current region, which results in poor ESD protection performance and high latchup risk. However, the strong snapback can be avoided in the EDNMOS device with high BDC. This implies that both the good ESD protection performance and the latchup immunity can be realized in terms of the EDNMOS by properly controlling its BDC.     

硅基光子材料和器件的进展

评述硅基光子材料和器件的进展，包括硅二极管的受激发射、具有量子结构的RCE(谐振腔增进型)光电二极管、MOS高频光调制器、SOI光开关阵列和可调谐波长滤波器，重点介绍低插入损耗、快响应的SOI基热光波导开关阵列的最新结果.以SOI为基片，成功地研制出带有全内反射(TIR)镜的重排无阻塞型光开关阵列，并首次研制出16×16阻塞型光开关阵列.在1.55pm波段，插入损耗和偏振相关性随着器件长度的增加而略微增大.如果器件的末端镀上抗反射膜，插入损耗会降低2～3dB，这些器件的上升和下降时间分别为2.1和2.3μs.