基于VHDL设计综合的扫描控制

运用VHDL硬件语言完成了激光成像雷达中扫描系统控制的描述。设计由ALTERA公司的MAX70010系列可编程逻辑器件实现。VHDL语言与可编程逻辑器件(CPLD)的结合使用,将传统上由硬件电路实现的功能转变为软件参与实现,从而易于修改和改进。给出了部分VHDL源代码描述,通过逻辑综合优化了设计,实现了设计的时序仿真,分析了VHDL语言在设计中应注意的一些问题。     

Duplication of directed graphs and exponential blow up of proofs

We develop a combinatorial model to study the evolution of graphs underlying proofs during the process of cut elimination. Proofs are two-dimensional objects and differences in the behavior of their cut elimination can often be accounted for by differences in their two-dimensional structure. Our purpose is to determine geometrical conditions on the graphs of proofs to explain the expansion of the size of proofs after cut elimination. We will be concerned with exponential expansion and we give upper and lower bounds which depend on the geometry of the graphs. The lower bound is computed passing through the notion of universal covering for directed graphs.

In this paper we present ground material for the study of cut elimination and structure of proofs in purely combinatorial terms. We develop a theory of duplication for directed graphs and derive results on graphs of proofs as corollaries.     

一种快速逻辑函数的优化方法

针对数字系统设计中计算机优化逻辑函数普遍存在操作复杂、存贮容量大、运算速度慢等问题,本文提出了易于计算机实现的优化方法,即:列表法和十进制表示的多维体运算结合起来求素项,选择极值法求最小覆盖的优化方法,并对循环函数进行处理.这种方法大大减少了存储容量、加快了运算速度,并且增大了程序的应用范围.大量的实验证明了该方法的正确性和易于计算机实现的有效性.因此,本文方法在数字系统EDA中具有广泛的应用前景.     

An efficient and high-speed VLSI implementation of optimal normal basis multiplication over GF(2m)

Finite field multiplication is one of the most important operations in the finite field arithmetic and the main and determining building block in terms of overall speed and area in public key cryptosystems. In this work, an efficient and high-speed VLSI implementation of the bit-serial, digit-serial and bit-parallel optimal normal basis multipliers with parallel-input serial-output (PISO) and parallel-input parallel-output (PIPO) structures are presented. Two general multipliers, namely, Massey–Omura (MO) and Reyhani Masoleh–Hassan (RMH) are considered as case study for implementation. These multipliers are constructed by using AND, XOR–AND and XOR tree components. In the MO multiplier, to have strong input signals and have a better implementation, the row of AND gates are implemented by using inverter and NOR components. Also the XOR–AND component in the RMH structure is implemented using a new low-cost structure. The XOR tree in both multipliers consists of a high number of logic stages and many inputs; therefore, to optimally decrease the delay and increase the drive ability of the circuit for different loads, the logical effort method is employed as an efficient method for sizing the transistors. The multipliers are first designed for different load capacitances using different structures and different number of stages. Then using the logical effort method and a new proposed 4-input XOR gate structure, the circuits are modified for acquiring minimum delay. Using 0.18 μm CMOS technology, the bit-serial, digit-serial and bit-parallel structures with type-1 and type-2 optimal normal basis are implemented over the finite fields GF(2²²⁶) and GF(2²³³) respectively. The results show that the proposed structures have better delay and area characteristics compared to previous designs.     

An introduction of logical entropy on sequential effect algebra

The main aim of this study was to introduce logical entropy on dynamical systems that their state spaces were sequential effect algebra. In this regard, logical partition was defined on sequential effect algebra and then based on logical partition concept, logical entropy on partitions, conditional logical entropy, and logical entropy on dynamical systems were introduced and their features were analyzed. In addition, it was proved that this entropy is an invariant object under isomorphism relation.     

Logical design and synthesis of indole-2,3-diones and 2-hydroxy-3(2H)-benzofuranones via one-pot intramolecular cyclization

A novel and attractive protocol to synthesis indole-2,3-diones and 2-hydroxy-3(2H)-benzofuranones and via copper(II) oxide catalyzed intramolecular cyclization is described. This method possesses functional-group compatibility, easy workup procedure, shorter reaction time and high yields.     

Logical inference approach to relativistic quantum mechanics: Derivation of the Klein–Gordon equation

The logical inference approach to quantum theory, proposed earlier De Raedt et al. (2014), is considered in a relativistic setting. It is shown that the Klein–Gordon equation for a massive, charged, and spinless particle derives from the combination of the requirements that the space–time data collected by probing the particle is obtained from the most robust experiment and that on average, the classical relativistic equation of motion of a particle holds.     

Logical effort based dynamic power estimation and optimization of static CMOS circuits

This paper introduces a simple and yet accurate closed-form expression to estimate the switching power dissipation of static CMOS gates. The developed model depends on normalizing a gate switching power to that of the unit standard inverter and it accounts for the effect of internodal capacitances. For different loads, gates, sizes and processes, the developed model shows a good agreement with Hspice simulations using BSIM3v3 and BSIM4 models for UMC 0.13 μm and Predictive high-k 45 nm processes, respectively. The average error introduced by the model for the considered scenarios is about 3.1%. Depending on the normalized switching power model, two power optimization techniques have been proposed in this paper. The first deals with transistor sizing problem and presents a scheme to size transistors according to a specific design goal. The second technique relies on the joint transistor sizing and supply voltage scaling for reducing the switching power dissipation under specific delay requirements. This technique exhibits superiority over the first for the considered technology processes: UMC 0.13 μm and the Predictive high-k 45 nm.     

MILP approach to pattern generation in logical analysis of data

Pattern generation methods for the Logical Analysis of Data (LAD) have been term-enumerative in nature. In this paper, we present a Mixed 0-1 Integer and Linear Programming (MILP) approach that can identify LAD patterns that are optimal with respect to various previously studied and new pattern selection preferences. Via art of formulation, the MILP-based method can generate optimal patterns that also satisfy user-specified requirements on prevalence, homogeneity and complexity. Considering that MILP problems with hundreds of 0-1 variables are easily solved nowadays, the proposed method presents an efficient way of generating useful patterns for LAD. With extensive experiments on benchmark datasets, we demonstrate the utility of the MILP-based pattern generation.     

Modelling either-or relations in integer programming

Logical relations occur frequently in integer programming problems and are modelled by introducing binary variables in association with linear expressions. Applications requiring constraints involving precedence, exclusion, implication and other conditions give rise to the logical relations OR and IMPLIES in the models. These relations will be considered in this paper from a modelling point of view and formulations investigated for situations where the logical variables link sets of integer variables. Valid inequalities (cuts) that can be added to a model will be developed for a number of the formulations and the computational benefits of these cuts will be considered from an experimental point of view by considering the performance of sets of problem instances. New formulations and combinations of older established formulations will be considered. It will be contended that tight formulations may not always be the most successful.