晶片传输系统中切边探测和预对准技术

介绍投影光刻机设备的晶片传输系统中切边探测和晶片预对准技术。     

Laser‐Induced Direct Lithography for Patterning of Carbon with sp3 and sp2 Hybridization

A new method of laser‐induced lithography for direct writing of carbon on a glass surface is described, in which deposition occurs from a transparent precursor solution. At the glass–solution interface where the laser spot is focused, a micro‐explosion process takes place, leading to the deposition of pure carbon on the glass surface. Transmission electron microscopy (TEM) analysis shows two distinct co‐existing phases. The dominant one shows a mottled morphology with diffraction typical of cubic (sp³) diamond. The other region shows an ordered array of graphene sheets with diffraction pattern typical of sp²‐bonded carbon. The sp³ crystallites range in size from 9 to 30 Å and are scattered randomly throughout the sample. A UV Raman spectrum shows a broad band at the location of the expected diamond peak, together with a peak corresponding to the graphite region. We conclude that the patterned carbon is composed of a mixture of nanocrystalline sp³ and sp² carbon forms.     

Dose control circuit for digital electrostatic electron-beam array lithography

This paper demonstrates a technique for controlling the electron emission of an array of field emitting vertically aligned carbon nanofibers (VACNFs). An array of carbon nanofibers (CNF) is to be used as the source of electron beams for lithography purposes. This tool is intended to replace the mask in the conventional photolithography process by controlling their charge emission using the “Dose Control Circuitry” (DCC). The large variation in the charge emitted between CNFs grown in identical conditions forced the controller design to be based on fixed dose rather than on fixed time. Compact digital control logic has been designed for controlling the operation of DCC. This system has been implemented in a 0.5 μm CMOS process. Chandra Sekhar A. Durisety received his B.E. (Hons.) Instrumentation from Birla Institute of Technology and Sciences, Pilani, India in 1997 and his M.S in Electrical Engineering from University of Tennessee, Knoxville in 2002. Since 2003, he has been working towards his Ph.D degree also in Electrical Engineering at Integrated Circuits and Systems Lab (ICASL), University of Tennessee, Knoxville. He joined Wipro Infotech Ltd, Global R & D, Bangalore, India in 1997, where he designed FPGA based IPs for network routers. Since 1999, he was involved in the PCI bridge implementation at CMOS chips Inc, Santa Clara, CA, and the test bench development for Sony’s MP3 player, while at Toshiba America Electronic Components Inc., San Jose, CA. His research interests include multi-stage amplifiers, data converters, circuits in SOI and Floating Gate Devices. Rajagopal Vijayaraghavan received the B.E degree in electronics and communication engineering from Madras University in 1998 and the M.S degree in electrical engineering from the University of Texas, Dallas in 2001.He is currently working towards the Ph.D degree in electrical engineering at the University of Tennessee. His research interest is in the area of CMOS Analog and RF IC design. His current research focuses on LNAs and VCOs using SOI based MESFET devices. Lakshmipriya Seshan was born in Trivandrum, India on April 30, 1979. She received her B.tech in Electronincs & Communication Engg from Kerala University, India in June 2000 and M.S in Electrical Engg from University of Tennessee in 2004. In 2004, she joined Intel Corporation as an Analog Engineer, where she is engaged in the design of low power, high speed analog circuits for various I/O interface topologies. Syed K. Islam received his B.Sc. in Electrical and Electronic Engineering from Bangladesh University of Engineering and Technology (BUET) and M.S. and Ph.D. in Electrical and Systems Engineering from the University of Connecticut. He is presently an Associate Professor in the Department of Electrical and Computer Engineering at the University of Tennessee, Knoxville. Dr. Islam is leading the research efforts of the Analog VLSI and Devices Laboratory at the University of Tennessee. His research interests are design, modeling and fabrication of microelectronic/optoelectronic devices, molecular scale electronics and nanotechnology, biomicroelectronics and monolithic sensors. Dr. Islam has numerous publications in technical journals and conference proceedings in the areas of semiconductors devices and circuits. Benjamin J. Blalock received his B.S. degree in electrical engineering from The University of Tennessee, Knoxville, in 1991 and the M.S. and Ph.D. degrees, also in electrical engineering, from the Georgia Institute of Technology, Atlanta, in 1993 and 1996 respectively. He is currently an Assistant Professor in the Department of Electrical and Computer Engineering at The University of Tennessee where he directs the Integrated Circuits and Systems Laboratory (ICASL). His research focus there includes analog IC design for extreme environments (both wide temperature and radiation immune), multi-gate transistors and circuits on SOI, body-driven circuit techniques for ultra low-voltage analog, mixed-signal/mixed-voltage circuit design for systems-on-a-chip, and bio-microelectronics. Dr. Blalock has co-authored over 60 published refereed papers. He has also worked as an analog IC design consultant for Cypress Semiconductor Corp. and Concorde Microsystems Inc.     

变频器在单张纸平版印刷机改造中的应用

本文主要介绍了变频器在国产单双色单张纸平版印刷机改造中的应用，以及对变频器的一些功能的要求。     

Spontaneous Formation of Ordered Lateral Patterns in Polymer Thin‐Film Structures

The understanding of the lateral morphology stability of thin polymer devices is of fundamental importance. In this work, the lateral morphology in a model system consisting of thin polymer films capped with thin metal layers on a Si substrate is investigated. When the model system is heated above a critical temperature, a characteristic surface topographic structure is observed that has a well‐defined periodicity but random orientation. It is shown that the minimum temperature, T_min, required for the surface pattern to be observed decreases with increasing polymer‐film thickness. Increasing either the metal‐ or polymer‐layer thickness increases the characteristic wavelength of the topography. It is believed that the dominating driving force for the surface corrugated‐pattern formation is the thermal‐expansion‐coefficient mismatch of the capping layer and the substrate. A theoretical model based on local bending of a thin, stiff surface film on a thin, elastic medium is used to provide a quantitative analysis of the surface morphology. The calculated minimum temperature required for the surface morphology and the periodicity of the surface patterns to form are in strong agreement with the experimental results. By contrast, systems with prefabricated topographic patterns within any of the three layers (polymer, metal, substrate) produce highly anisotropic surface topographies aligned perpendicular to the prefabricated topographic structure. It is also found that, in a model system with pre‐patterned polymer films, a much higher critical temperature is required for the surface morphology to be observed. The changes in apparent stability and morphological orientation in the pre‐patterned systems can be understood as a result of the anisotropic release of the lateral surface stress during the heat treatment.     

极紫外光刻真空工件台技术研究

在极紫外光刻系统中,真空工件台的运行精度、速度、加速度以及动态定位和扫描同步性能是影响整机成像质量、套刻精度和产率的重要因素。结合极紫外光刻机的工作原理和发展现状,论述了极紫外光刻机真空工件台系统的特征、组成及其关键技术。     

一种用于LSPR传感器的准正方型银纳米颗粒阵列制备

首先控制聚苯乙烯纳米球(PS球)乳液在基片上的干燥温度,采用自组装方法,使用单一粒径的PS球制备出单层的PS球亚稳态正方排列结构模板。然后,在模板上通过磁控溅射法沉积一层银膜。利用纳米球光刻技术,去掉PS球模板得到二维正方点阵排列的准正方形银纳米颗粒阵列结构。     

极紫外光刻系统物镜光学元件的支撑与分析

介绍了极紫外光刻系统物镜光学元件的支撑原理和支撑要求,分析了符合运动学支撑要求的物镜支撑结构和面形检测用支撑结构;针对支撑结构性能和支撑方案中关键问题进行了深入研究,并提出了相应的解决方案。最后建立了支撑结构的有限元模型,并在此基础上进行了重力场中的镜体变形分析和温度场作用下系统的热变形分析。分析结果表明,检测用支撑与实际用支撑两种结构在重力环境下支撑出的元件面形基本相同,面形相差0.0026nm(RMS);温控范围为0.05℃时,由机械结构热变形引起的镜体面形变化在0.001nm(RMS)量级。研究结果表明,运动学物镜元件支撑结构能够满足极紫外光刻系统对于物镜机械支撑结构的要求。     

光刻设备中工件台激光测长原理

通过对双频激光干涉仪的原理、结构、双频产生机理进行分析,阐述激光干涉仪在光刻设备中的实际应用,探讨激光干涉仪技术。     

Efficient electron beam condensing for low-energy microcolumn lithography

Low-energy electron beam lithography has been performed with a microcolumn by adopting a new technique that condenses the electron beam efficiently. To increase the probe current while keeping the kinetic energy of electrons sufficiently low, the negative or positive bias has been applied to the accelerator electrode, which reduces the divergence of the electron beam and hence makes more electrons pass through the microcolumn. With this technique, the probe current more than 1 nA has been achieved, which is large enough for the practical application of microcolumn lithography even when the kinetic energy of electrons is as low as 160 eV. The results of microcolumn lithography by using the condensed electron beam with a low-energy of 160 and 327 eV are also presented.