玻璃纤维布内中空纤维丝的检测

介绍了玻璃纤维布内中空纤维丝的检测方法。     

基于Agilent-VEE平台的测试系统设计与应用

美国安捷伦公司(原惠普公司)的Agilent-VEE，NI公司的Lab VIEW和Lab Windows／CVI开发软件等是国际上公认的优秀的虚拟仪器开发平台软件，人们对以应用后两者开发测试系统比较了解，但对VEE在测试系统中的应用少有介绍。本文介绍基于Agilent-VEE平台和GPIB总线的实用测试系统的组成、特点及仪器控制方式。     

Signal Integrity: Fault Modeling and Testing in High-Speed SoCs

As we approach 100 nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-on-chips. Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliability problems. In this paper, we first define a model for integrity faults on the high-speed interconnects. Then, we present a BIST-based test methodology that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz system-on-chips. Using an inexpensive test architecture the integrity information accumulated by these special cells can be scanned out for final test and reliability analysis.     

The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs

Modular testing is an attractive approach to testing large system ICs, especially if they are built from pre-designed reusable embedded cores. This paper describes an automated modular test development approach. The basis of this approach is that a core or module test is dissected into a test protocol and a test pattern list. A test protocol describes in detail how to apply one test pattern to the core, while abstracting from the specific test pattern stimulus and response values. Subsequent automation tasks, such as the expansion from core-level tests to system-chip-level tests and test scheduling, all work on test protocols, thereby greatly reducing the amount of compute time and data involved. Finally, an SOC-level test is assembled from the expanded and scheduled test protocols and the (so far untouched) test patterns. This paper describes and formalizes the notion of test protocols and the algorithms for test protocol expansion and scheduling. A running example is featured throughout the paper. We also elaborate on the industrial usage of the concepts described.     

铁路电力试验车软件的设计与实现

介绍了铁路电力试验车软件的设计思想、框架结构及其总体控制策略 ,并就其中的测试程序、数据库管理系统、串口通讯程序、复杂式样报表生成和系统安装程序的设计策略作了叙述。     

Model validation and model structure determination

This paper gives a tutorial overview of basic approaches for model validation and model structure determination.Work partially supported by the Swedish Research Council for Engineering Sciences under contract 98-654.     

托卡马克工程试验混合堆等离子体性能的等值线图分析

本文简要叙述托卡马克工程试验混合堆等离子体概念设计的物理基础,对等离子体性能进行了等值线图(Plasma Operation Contour)分析。根据工程试验混合堆的要求,得出一组等离子体参数。     

电视机监督检验电磁兼容结果分析和对策

本文讨论了电磁兼容对电视机的技术要求和相应对策。     

Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores

This paper introduces a new concept of testability called consecutive testability and proposes a design-for-testability method for making a given SoC consecutively testable based on integer linear programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from test pattern sources (implemented either off-chip or on-chip) consecutively at the speed of system clock. Similarly the test responses are propagated to test response sinks (implemented either off-chip or on-chip) from the core outputs consecutively at the speed of system clock. The propagation of test patterns and responses is achieved by using interconnects and consecutive transparency properties of surrounding cores. All interconnects can be tested in a similar fashion. Therefore, it is possible to test not only logic faults but also timing faults that require consecutive application of test patterns at the speed of system clock since the consecutively testable SoC can achieve consecutive application of any test sequence at the speed of system clock.