移动通信网中端端认证方案的研究

现有的数字移动通信网中提供移动用户与基地地间的保密通信服务,移动用户的间的端端保密通信在移动通信网中还是一个新问题。本文分析了已有端端认证方案的安全性,提出了一种单钥体制域内端端认证方案和一种单钥／双钥混合体制域间端端认证方案。分析结果结果：新方案不仅安全性很高,而且利用于移动端的实现,也便于网络端的密钥管理。     

基于Hadoop的气象数据分布式存储技术研究

针对目前气象数据存储所面临的海量扩张、高并发读写、结构化和非结构化数据并存以及长时间序列和大数据集检索效率低下等问题,提出了以Hadoop开源框架为基础的气象数据分布式存储方案.通过对气象数据自身属性和特点进行分析,得出了气象数据在经过充分优化的基础上,在分布式存储框架中具有很强的适应性和规模化应用的潜力;并在HBas...     

Compact Bandpass Filter with high selectivity and wide stopband using Slotted Stepped-Impedance Resonator

In this paper, a Slotted Stepped-Impedance Resonator (SSIR) is proposed. Due to the slots in the low-impedance section of the conventional SIR, the new resonator has a lower fundamental resonance f0 and can provide a potential finite transmission zero fz close to f0. Based on the proposed SSIR, a fourth-order Chebychev BandPass Filter (BPF) is designed at f0=1 GHz. The measured results show that a better than –65 dB rejection is achieved on both the lower and the upper stopband. Moreover, the new filter has a wide –30 dB rejection upper stopband from 1.13f0 to 6.52f0. The fab-ricated filter exhibits a size of The new filter has a planar topology and is easily integrated with modern portable communication systems.     

一种任意维空域最小二乘算法的硬件实现方法

在自适应滤波算法中,空域递推最小二乘(RLS)算法以其较快的收敛速度以及能计算出精确的最佳滤波器系数等优势得到了广泛的运用。但是由于该算法较为复杂,计算量大,因此硬件实现时耗费资源多,难度大。提出了一种任意维空域递推最小二乘算法的FPGA(现场可编程门阵列)实现的方法,该方法可以在硬件结构中使用较少的乘法器和寄存器进行任意维空域递推最小二乘运算,从而解决维数变多后资源不够用的问题。     

网络环境中基于RSA算法的密钥托管

密钥托管密码体制不仅能保护用户的隐私权,同时允许法律授权下的监听。本文提出了在网络环境中基于RSA算法的一种密钥托管体制。系统中有一可信中心,为每一用户指定n个委托人,每一委托人为网络中一服务器。可信中心按(t,n)门限方案为n个委托人分配恢复用户密钥的部分能力。用户在系统中广播自己经过加密的密钥时,仅当至少有t个委托人联合起来才能实施对用户的监听。     

一种新的基于身份的安全组播密钥协商方案

密钥管理是安全组播的难点。该文提出了一个新的基于身份的密钥协商方案,并具体地分析了子组之间的通信过程,以及组成员动态变化时密钥的更新过程。结果表明该方案满足密钥协商安全性要求,且在降低计算和通信代价方面取得了较好的效果。     

变结构／变初值准混沌滚动密钥产生器

本文首先指出传统的滚动密钥产生器，在滚动密钥生成的过程中，状态转移函数和输出函数的结构初值及其状态初值都是固定的不变的，因此，利用在道中截取足够长的数据，原则上，总是可以破译的。鉴于此，我们在数字或准混沌意义上，采用综合算法提出了变结构／变初值准混沌滚动密钥产生器，使之在滚动密钥的生成过程中，状态转移函数和输出函数每一个字节都更新一次结构初值和状态初值，且永不重复、不可预测。在未建立综合数字之前，     

基于肠道菌群探讨葛根芩连汤治疗湿热型2型糖尿病研究进展*

摘 要: 近年来世界范围内2型糖尿病(Diabetes Mellitus type 2,T2DM)的发病率不断上升。微生态学研究证实,T2DM疾病的发生与肠道菌群数量及比例的失调有很大的关联性,这成为研究热点。现有实验发现:肠道菌群紊乱可通过短链脂肪酸学说、胆汁酸代谢学说、内毒素学说、支链氨基酸学说等机制来影响T2DM的发生发展。湿热证T2DM患者在临床最为常见,该类患者胰岛素抵抗最为严重,而动物实验研究发现葛根芩连汤可通过特定的分子机制及通路作用于肠道菌群,通过调节胰岛β细胞的功能、提高胰岛素敏感性、减轻氧化应激反应,从而调节血糖,减轻胰岛素抵抗,为临床治疗T2DM患者提供更科学的依据。但由于菌群数量庞杂,现有数据多偏重于动物实验,且研究菌群特异性不足,为此今后需进一步加强对T2DM特定菌群的研究,以及增加临床大样本数据统计。     

Performance of a new decoding method used in open-loop all-optical chaotic communication system

A new decoding method with decoder is used in open-loop all-optical chaotic communi-cation system under strong injection condition. The performance of the new decoding method is nu-merically investigated by comparing it with the common decoding method without decoder. For new decoding method, two cases are analyzed, including whether or not the output of the decoder is ad-justed by its input to receiver. The results indicate the decoding quality can be improved by adjusting for the new decoding method. Meanwhile, the injection strength of decoder can be restricted in a certain range. The adjusted new decoding method with decoder can achieve better decoding quality than decoding method without decoder when the bit rate of message is under 5 Gb/s. However, a stronger injection for receiver is needed. Moreover, the new decoding method can broaden the range of injection strength acceptable for good decoding quality. Different message encryption techniques are tested, and the result is similar to that of the common decoding method, indicative of the fact that the message encoded by using Chaotic Modulation (CM) can be best recovered by the new decoding method owning to the essence of this encryption technique.     

Low-power survivor memory architecture for DFSE in 1000BASE-T transceiver

A novel approach to survivor memory unit of Decision Feedback Sequence Estimator （DFSE） for 1000BASE-T transceiver based on hybrid architecture of the classical register-exchange and trace-back methods is proposed. The proposed architecture is investigated with special emphasis on low power and small decoder latency, in which a dedicated register-exchange module is designed to provide tentative survivor syml~ols with zero latency, and a high-speed trace back logic is presented to meet tile tight latency budget specified for 1000BASE-T transceiver. Furthermore, clock-gating register banks are constructed for power saving. VLSI implementation reveals that, the proposed architecture provides about 40% savings in power consumption compared to the traditional register-exchange architecture.