Acoustic characteristics of reticent speech

Reticent speakers differ from nonreticent speakers in vocal characteristics, such as fundamental frequency, frequency range, fluency, and intensity, which prompt negative impressions on the part of listeners. Waveform and spectrographic analyses were performed on the vocal cues of 19 reticent and nonreticent subjects (57 speech samples). Statistically significant differences were found in fluency between reticent and nonreticent speech. Reticent male speakers also showed significantly higher F₀, whereas reticent female speakers demonstrated narrower frequency range. Identification and analysis of these characteristics are required for effective remediation.     

RC和LC延迟触发器

对大功率延迟触发器中使用的氢闸流管的栅极点火特性,特别是延迟时间分散度做了比较细致的研究,对延迟时间做了理论计算,理论和实验符合得很好。本实验所用的延迟触发器输出电压幅度为3kV,电阻性负载的输出功率为十分之几兆瓦,最大时延50μs,改进型RC延迟器的时间分散度小于70ns,LC延迟触发器的时间分散度小于20ns。最后对进一步提高延迟时间的稳定性提出了若干改进措施。     

Intraproduction variability in jitter measures from elderly speakers

This study examined intraproduction variability in jitter measures from elderly speakers' sustained vowel productions and tried to determine whether mean jitter levels (percent) and intraspeaker variability on jitter measures are affected significantly by the segment of the vowel selected for measurement. Twenty-eight healthy elderly men (mean age 75.6 years) and women (mean age 72.0 years) were tape recorded producing 25 repeat trials of the vowels /i/, /a/, and /u/, as steadily as possible. Jitter was analyzed from two segments of each vowel production: (a) the initial 100 cycles after 1 s of phonation, and (b) 100 cycles from the most stable-appearing portion of the production. Results indicated that the measurement point selected for jitter analysis was a significant factor both in the mean jitter level obtained and in the variability of jitter observed across repeat productions.     

A PVT aware differential delay circuit and its performance variation due to power supply noise

Delay circuits are one of the key components in time domain blocks such as pulse width modulator. This work describes the working of a differential delay circuit under process, voltage and temperature. The proposed design is also coupled to a typical power delivery network (PDN) and a central processing unit (CPU) core ramping current from 0 A to 10–40A in 10 ns Simulated in a 90-nm CMOS technology and power supply voltage (Vdd) of 1.1 V, the post-layout delay was noted to be 227 ps During this time, differential signals at the input are switching at 1GHz while the rise, fall times are about 0.1ns The power thus dissipated corresponds to 235 μW. But, delay changes by about 0.4–0.9 ps at every process corner while temperature increases by 1^OC. The corresponding variation for 1mV drop in power supply voltage is 0.1–0.4ps In addition to that, a change in temperature enables the average power to fluctuate between 192.8 and 264μW, whereas, 0.6μW for 1mV drop in power supply voltage. The study of 500 runs Monte-Carlo analysis for a NN process indicates an almost identical behavior with the no skew data in post-layout. The rms jitter is within 0.01–0.3ps while the delay per mV change in power supply is 0.21 ps/mV. But a sudden current drawn by the CPU causes the voltage V_P close to the die to oscillate. This enables the delay to vary than those obtained with zero power supply noise. The sudden current also introduces jitter in the output swing. The jitter so induced varies linearly with the AC first droop.     

兆伏级重复频率三电极气体开关工作特性研究

 以“CHP01”加速器为实验平台，对自行研制的重复频率三电极气体开关的工作特性开展了实验研究，并对实验结果进行了分析。研究结果表明：开关在自击穿工作下的工作稳定性远小于触发工作时，开关工作范围与触发针位置和气压等因素有关；开关电压选择在自击穿电压的大约80％时，开关抖动小、误触发率低，具有较好的工作特性。     

基于延迟锁相环和锁频环结构的全数字同步倍频器

针对现有基于PLLs/DLLs的全数字化同步倍频器结构存在的不足,本文提出了基于一种双环结构的全数字同步倍频器。它由延迟锁相环和锁频环共享一个共同的参考时钟信号(FREF)构成,不需要任何模拟组件。它可以采用Verilog-HDL语言设计,可在Altera DE2-70开发板上实现合成,而且可以很容易地适应于不同的FPGA系列以及作为一个集成电路实现,同时也可用于为分布式数字处理系统以及片上系统的片内/片间通信提供时钟参考;实验结果表明,本文所提出的结构相比于现有的结构,能够获得更高频率的输出时钟信号,提供更好的频率分辨率、更好的抖动性能和高倍乘因子。     

An improved adaptive threshold modulation method for jitter reduction in SDH/SONET

Adaptive threshold modulation is widely adopted in SDH/SONET network for pointer processing and mapping. When the processing rate is very high, the performance of an all digital implementation is limited by the phase error resolution. Phase error re-sampling technique is adopted here for the all digital implementation of an improved adaptive threshold modulation, which can work in greatly reduced operating speed with high jitter and wander performance. The improved method is adopted in AU-4 and TU-12 pointer processors and the simulated performance is given.     

一种级联结构的高阶全数字锁相环

本文给出了一种高阶全数字锁相环的级联结构形式,它通过结构简单的全数字一阶环的级联来实现高阶环路。它避免了通常的高阶锁相环中较复杂的数字滤波器,实现简单,易于集成。本文介绍了级联全数字二阶环的原理和实现,对其性能进行了理论分析和计算机仿真,最后给出一个应用实例。     

200kV/100kA低抖动环轨式多通道场畸变开关

 研制了一种200kV/100kA环轨式场畸变开关。对该开关以Ar，N₂，SF₆及SF₆/N₂，SF₆/Ar 混合气为工作介质的耐压及触发性能研究结果表明：该开关耐压最大偏差小于自击穿电击的4%；欠压比大于等于自击穿电击80%时，抖动极差小于2ns，标准方差抖动小于等于1ns；实现了多通道导通，通道数大于等于3；开关工作范围极大，在欠压比大于等于自击穿电击20%时抖动极差小于2.85ns。     

对基于DLL和PLL的射频CMOS振荡器的相位抖动比较

通过对 PL L 和 DL L 相位抖动的比较 ,结合 DL L 倍频器的结构特点 ,得出了一个有用的公式 ,这个公式可以用于在 PL L 和 DL L 两种结构中选择出一个最佳方案 ,使得在使用 CMOS工艺实现频率合成器时能够得到最佳的功耗和相位抖动的折衷 .对于倍频系数很大的倍频器宜采用基于 PL L 的结构 ,这样可以消耗较少的功率 ;而对于较小的倍频系数的倍频器要采用基于 DL L 的结构 ,这样相位抖动特性将非常优良